[DRC NSTD-1] Unspecified I/O Standard: 39 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: dout_1_reg[15:0], dout_2_reg[15:0], clk, clk_axi, rst_l [DRC UCIO-1] Unconstrained Logical Port: 39 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: dout_1_reg[15:0], dout_2_reg[15:0], clk, clk_axi, rst_l The error messages seem to be implying that there is some top level output signal that is not routed to a pin. However, the signals in question are all internal (for example clk is connected between a module that I created and a clock wizard, and rst_l is connected between the zynq processor and my module), and they are not even referenced in the top level wrapper. There are four signals that are routed to pins referenced in the XDC, and none of these signals are generating errors. After implementation, I can see that the signals that are not considered external in the wrapper are labeled with the port symbol in the implemented design. I receive warnings during synthesis and implementation, and while generating the bitstream, the design fails. Does anyone have any idea as to what could be causing this?

Vivado throwing error because no port location is specified for signals that are not top level

[DRC NSTD-1] Unspecified I/O Standard: 39 out of 43 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: dout_1_reg[15:0], dout_2_reg[15:0], clk, clk_axi, rst_l
[DRC UCIO-1] Unconstrained Logical Port: 39 out of 43 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: dout_1_reg[15:0], dout_2_reg[15:0], clk, clk_axi, rst_l

The error messages seem to be implying that there is some top level output signal that is not routed to a pin. However, the signals in question are all internal (for example clk is connected between a module that I created and a clock wizard, and rst_l is connected between the zynq processor and my module), and they are not even referenced in the top level wrapper. There are four signals that are routed to pins referenced in the XDC, and none of these signals are generating errors.

After implementation, I can see that the signals that are not considered external in the wrapper are labeled with the port symbol in the implemented design.

I receive warnings during synthesis and implementation, and while generating the bitstream, the design fails.

Does anyone have any idea as to what could be causing this?