People say it is "The programming of the FTDI chip on the Ultra96 JTAG/UART adapter is proprietary to Xilinx. Avnet cannot share this information publicly". AFAIK, SW2 JTAG mode is regarding to pure JTAG probe without using ftdi usb to jtag chip.
Yes, but you can access it over JTAG via Vivado lab XSDB or Vitis XSCT. You can also write a small program for the flash to configure that register via ARM SW on "normal" power-up, then the next reset will be JTAG boot.
my goal is handling blank zynqmp without using xilinx tools, just with general gnu arm tools, since zynq soc is cpu oriented designs, not like last generation powerpc soc.
