I am trying to get the VxWorks image on U boot for the ZUB1CG board, but I am getting the below error again and again.
Unknown exception
Exception Syndrome Register(ESR): 0x02000000
Exception Address: 0xffffffff802a8218
Process State Register(PSTATE): 0x00000044
Task: 0xffffffff80997000 "tRootTask"
0xffffffff80997000 (tRootTask): task 0xffffffff80997000 has had a failure and has been stopped.
0xffffffff80997000 (tRootTask): The task has been terminated because it triggered an exception that raised signal 4.
I am using below DTS file for running it on Uboot but am getting the above error. Please let me know the cause and solution to issue.
/dts-v1/;
#include "prjParams.h"
/ {
compatible = "xlnx,zynq-ultrascale-mpsoc";
model = "Xilinx ZCU102";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&intc>;
cpus
{
#address-cells = <2>;
#size-cells = <0>;
cpu@0
{
device_type = "cpu";
reg = <0 0>;
};
cpu@1
{
device_type = "cpu";
reg = <0 1>;
};
};
aliases
{
serial0 = &uart0;
ethernet3 = &gem3;
};
memory@0
{
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
//<0x8 0x00000000 0x0 0x80000000>;
};
chosen
{
bootargs = "gem(0,0)host:vxWorks h=192.168.1.2 e=192.168.1.6:ffffff00 g=192.168.1.1 u=target pw=vxTarget";
stdout-path = "serial0";
};
soc:soc
{
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
intc: interrupt-controller@f9010000
{
compatible = "arm,gic","arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0 0xf9010000 0x0 0x1000>, /* GICD */
<0x0 0xf9020000 0x0 0x20000>, /* GICC */
<0x0 0xf9040000 0x0 0x20000>, /* GICH */
<0x0 0xf9060000 0x0 0x20000>; /* GICV */
max-int-lvl = <190>;
status = "okay";
};
clk: clk_ctrl@fd1a0000
{
compatible = "xlnx,zynqmp-clock";
reg = <0x0 0xfd1a0000 0x0 0x1000>, /* CRF_APB module */
<0x0 0xff5e0000 0x0 0x1000>; /* CRL_APB module */
pll-status-regs = <0x44 0x40>; /* CRF, CRL PLL status registers */
status = "okay";
ps_ref_clk: ps_ref_clk
{
#clock-cells = <0>;
compatible = "xlnx,zynqmp-fixed-clk";
clock-frequency = <33330000>;
};
iopll_clk: iopll_clk
{
#clock-cells = <0>;
compatible = "xlnx,zynqmp-pll-clk";
clocks = <&ps_ref_clk>;
register = <1 0x20>;
lock-shift = <0>;
};
gem3_ref_div_clk: gem3_ref_div_clk
{
#clock-cells = <0>;
compatible = "xlnx,zynqmp-div-clk";
clocks = <&iopll_clk>;
register = <1 0x5c>;
div = <8 0x3f 0>,
<16 0x3f 0>;
enable = <25 0x03 0x03>;
};
uart0_ref_div_clk: uart0_ref_div_clk
{
#clock-cells = <0>;
compatible = "xlnx,zynqmp-div-clk";
clocks = <&iopll_clk>;
register = <1 0x74>;
div = <8 0x3f 0>,
<16 0x3f 0>;
enable = <24 1 1>;
};
};
uart0: serial@ff000000
{
compatible = "xlnx,xuartps";
reg = <0x0 0xff000000 0x0 0x1000>;
clocks = <&uart0_ref_div_clk>;
clock-frequency = <100000000>;
interrupts = <53 0 4>;
interrupt-parent = <&intc>;
status = "okay"; /* set "okay" to enable access */
};
timer0: timer
{
compatible = "arm,arm-gen-timer", "arm,armv8-timer";
interrupts = <29 1 1>, /* secure physical timer PPI */
<30 1 1>, /* non-secure physical timer PPI */
<27 1 1>; /* virtual timer PPI */
interrupt-parent = <&intc>;
status = "okay";
};
gem3: ethernet@ff0e0000
{
#size-cells = <0>;
#address-cells = <1>;
compatible = "xlnx,zynqmp-gem";
reg = <0x0 0xff0e0000 0x0 0x1000>;
clocks = <&gem3_ref_div_clk>;
bus-width = <64>;
#ifdef XLNX_ZYNQ_END_BD_RX_NUM
rx-bd-num = <XLNX_ZYNQ_END_BD_RX_NUM>;
#endif /* XLNX_ZYNQ_END_BD_RX_NUM */
#ifdef XLNX_ZYNQ_END_BD_TX_NUM
tx-bd-num = <XLNX_ZYNQ_END_BD_TX_NUM>;
#endif /* XLNX_ZYNQ_END_BD_TX_NUM */
local-mac-address = [ 00 0A 35 11 22 36 ];
interrupts = <95 0 4>;
interrupt-parent = <&intc>;
status = "okay"; /* set "okay" to enable access */
phy-handle = <&phy3>;
phy3: ethernet-phy@c
{
compatible = "tiDpPhy";
reg = <0x0c>;
rgmii-delay = <0x3>;
rx-internal-delay = <0x8>;
tx-internal-delay = <0xa>;
fifo-depth = <0x1>;
};
};
};
};