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PL core UART16550

Yaroslav

Hello,

I'm seeking assistance with configuring the AXI-based UART16550 IP Core in Vivado for ZUBoard 1G evaluation board.

I have successfully added the axi_uart16550_0 block in Vivado and exported the design to Vitis as an XSA file.

However, when running the provided example applications from the BSP (which include a self-test based on internal loopback), the application crashes, and the self-test fails.

Additionally, when I attempt to manually write to the UART's address space (0xA0000000), the write operation does not seem to work correctly, leading me to believe that there may be an issue with the hardware or configuration that is incompatible with the BSP's UART16550 settings.

Could anyone provide documentation or guidance on how to properly configure the AXI UART16550 IP Core in Vivado and ZUBoard 1G specific configuration?

Any insights into why the self-test might be failing or why the manual writes to the UART address space are not functioning correctly would be greatly appreciated.

Thank you!

  • 0

    Can you write and read the scratch register?  If not, you might not be running the bitfile that contains the UART16550.  The xparameters.h file in the platform should have constants related to the UART16550.

  • 0 in reply to padudle

    I have verified that all the related UART16550 addresses are defined correctly in xparameters.h.
    However, when I access the memory at 0xa0000000, it appears corrupted. I can read from this memory, but I am unable to write to it. The values in the entire address space at 0xa0000000 are either 0x00000000 or 0xffffffff.

    I suspect the issue might be related to the configuration of clocks or reset signals on the board, possibly involving the correct clock or reset signals connection to the FPGA. Could you provide assistance or guidance to resolve this issue?