https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboarden-USTelligent Community 12Tue, 05 May 2026 19:39:06 GMThttps://community.element14.com/thread/56766?ContentTypeID=0Mon, 16 Mar 2026 17:50:25 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f54104f3-0e4c-40da-bcb7-c11b0a66c3e9Tim50004https://community.element14.com/thread/56766?ContentTypeID=0https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-example/rss?ContentTypeId=0<p>Hi has anyone tried to build linux/uboot for the 1CG using the 2025.2 AMD EDF?</p> <p>I&#39;ve recently had an opportunity to dig my board out again and I&#39;m trying to run it using the latest toolchains as petalinux is being deprecated.</p> <p>My previous toying with this were simple ones based on the Adam Taylor ones back in 2023 using petalinux loaded via tftpboot.</p> <p></p> <p>I&#39;ve regenerated the XSA and Vitis artifacts using the 2025.2 Vivado and Vitis applications but trying to get a successful Linux/u-boot build via AMD EDF v2025.2 seems to be eluding me.</p> <p>Generating the SDT from the XSA appears to go OK but building eventually fails - it seems many things are trying to be built that aren&#39;t needed e.g.(mali GPU) so I&#39;ve ended up with a lot of things modified in my local.conf and still no success which makes me think it&#39;s not correctly targetting the board.</p> <p>meta-avnet doesn&#39;t appear to be updated for some time.</p>https://community.element14.com/thread/235374?ContentTypeID=1Tue, 05 May 2026 19:39:06 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:5919abd0-c4d1-4f2f-8b9d-b7bf35688204thill0https://community.element14.com/thread/235374?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-example/rss?ContentTypeId=0<p>Tim, I sent you a friend request so I can message you directly.</p><div style="clear:both;"></div>https://community.element14.com/thread/235372?ContentTypeID=1Tue, 05 May 2026 19:18:16 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f2224c25-239c-4c0e-98ae-8b2666ec1029Tim50001https://community.element14.com/thread/235372?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-example/rss?ContentTypeId=0<p>Hi <a href="https://community.element14.com/members/thill">thill</a>&nbsp;yeah that would be really interesting to see what you&#39;ve got!</p><div style="clear:both;"></div>https://community.element14.com/thread/235371?ContentTypeID=1Tue, 05 May 2026 19:00:43 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:75a00a3b-44f1-4333-912a-8efa6b8e20e4thill1https://community.element14.com/thread/235371?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-example/rss?ContentTypeId=0<p>Hi there, I&#39;m an Avnet FAE and I built an EDF platform for ZUBoard using Codex. I&#39;m new to EDF so it&#39;s hard to judge the quality of the result myself but it does boot, and I have terminal access via screen, ssh, and can ping both directions. I&#39;m still working on developing this build so if this work would be useful for you guys I&#39;m happy to share.</p><div style="clear:both;"></div>https://community.element14.com/thread/234479?ContentTypeID=1Wed, 18 Mar 2026 21:02:43 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:6c0ff19b-8627-4a92-9fe8-8ac179579db7iksevas1https://community.element14.com/thread/234479?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-example/rss?ContentTypeId=0<p>Unfortunately, we have not extended the support for the ZUBoard to 2025.2 yet and we have not attempted to work within the new AMD EDF process. The last support for meta-avnet is 2024.2 which should be translatable/importable to 2025.2 using the older flow.</p><div style="clear:both;"></div>https://community.element14.com/thread/234447?ContentTypeID=1Mon, 16 Mar 2026 16:34:43 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b29604dd-8914-4171-bcf5-d8d8aa5b32ecsalasidis0https://community.element14.com/thread/234447?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56275/zub1cg---xdc-file/rss?ContentTypeId=0<p>As I said, I am new to this, so it would be nice if I could have an example application as a starting point.&nbsp;</p> <p></p> <p>Is it possible to have one that uses the port with an if the shelf product (an ADC using syzygy)?</p> <p></p> <p>If not at least show me how to define done if the lvds pins and the plain io pins, and I can do the rest.</p> <p>Thanks</p><div style="clear:both;"></div>https://community.element14.com/thread/56275?ContentTypeID=0Tue, 14 Oct 2025 00:33:26 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:2e10edfe-13eb-4847-8cae-5be7c0be3a56salasidis4https://community.element14.com/thread/56275?ContentTypeID=0https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56275/zub1cg---xdc-file/rss?ContentTypeId=0<p>Is there a ready made .xdc file somewhere where this can be downloaded.</p> <p></p> <p>I am used to the Digilent boards where all the files were provided for all their boards.</p> <p></p> <p>Thanks</p>https://community.element14.com/thread/234446?ContentTypeID=1Mon, 16 Mar 2026 16:25:43 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:178a695a-0ac7-41c3-8430-9518433fca23iksevas1https://community.element14.com/thread/234446?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56275/zub1cg---xdc-file/rss?ContentTypeId=0<p>Unfortunately, the HSIO interface is generic so adding something to the BDF which could be defined as any interface that fits the expansion connector isn&#39;t a proper setting. If you have a module identified to use with the expansion connector, I suggest you then implement the interface needed for that particular interface in the block design standalone. You will either need to implement either your own IP or IP specific to the interface, ie - I2C, SPI, etc. You will also need to map those interfaces to external pins and provide constraints to implement it properly. The schematic for this board is available so any IO not presented in the BDF can be mapped to an XDC file.</p><div style="clear:both;"></div>https://community.element14.com/thread/234419?ContentTypeID=1Sat, 14 Mar 2026 20:19:13 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:424f1b3a-ec45-4ecc-86ab-f58e6333712csalasidis1https://community.element14.com/thread/234419?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56275/zub1cg---xdc-file/rss?ContentTypeId=0<p>The project was on a back burner for a while. Is there an example application of how to create the xdc pin mappings for the SYZYGY ports, and how to use them. I have found no example projects, or any definitions. The Board BDF file that is installed in Vivado only has some serial interfaces, buttons and LEDs defined, and not much else.<br /><br />New to using this, so sorry if the solution is obvious</p><div style="clear:both;"></div>https://community.element14.com/thread/56654?ContentTypeID=0Tue, 10 Feb 2026 10:03:12 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:776a1446-3d28-4302-9ab6-afc97d8a3410tstern0https://community.element14.com/thread/56654?ContentTypeID=0https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56654/zuboard-1cg---vitis-debugging-halts-when-communicating-with-gpio-over-at-pl-side/rss?ContentTypeId=0<p>I&#39;ve setup a minimal project in Vivado, basically I only have the a GPIO block connected to one of the RGB LEDs on the board:</p> <p><img style="max-height:360px;max-width:640px;" src="https://community.element14.com/resized-image/__size/1280x720/__key/communityserver-discussions-components-files/366/pastedimage1770717421781v1.png" alt=" " /></p> <p>Next, I tried modifying an example code so I can toggle the LED, but once I execute a command that tried reading or writing to the PL side (AXI?) the debugging halts and I must stop debugging to reset the system. The hardware export from Vivado includes the bit file.</p> <p>Here is the code that I&#39;m running, it will hang on:&nbsp;XGpio_SetDataDirection(&amp;Gpio, 1, 0);</p> <p>I&#39;ll appreciate it greatly if anyone could point out what&#39;s wrong here. I&#39;m using the latest Vivado &amp; Vitis.</p> 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0%20%20%20%2A%20Read%20the%20state%20of%20the%20data%20and%20verify.%20If%20the%20data%0D%0A%20%20%20%20%20%20%20%20%20%2A%20read%20back%20is%20not%20the%20same%20as%20the%20data%20written%20then%0D%0A%20%20%20%20%20%20%20%20%20%2A%20return%20FAILURE.%0D%0A%20%20%20%20%20%20%20%20%20%2A%2F%0D%0A%0D%0A%20%20%20%20%7D%0D%0A%20%20%20%20return%20XST_SUCCESS%3B%0D%0A%7D]&nbsp;</p>https://community.element14.com/thread/56626?ContentTypeID=0Fri, 30 Jan 2026 07:01:44 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:e5bb83a3-305f-40f4-b292-654578a9f9faMATRIX787814https://community.element14.com/thread/56626?ContentTypeID=0https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>Hello,</p> <p></p> <p>&nbsp; &nbsp; &nbsp; &nbsp;I have been working on a custom AXI4 Lite I2C core for the ZuBoard 1CG on board temp sensor.&nbsp; The best I can do is read back a value of 0x00 for the WHO_AM_I register.&nbsp; It should be 0xA0.&nbsp; Since Xilinx&#39;s AXI4 IP creator is broken, I have created a custom AXI4 protocol.&nbsp; I need help understanding what the problem with my design is.&nbsp; I do not know if it is with my VHDL, or my C.&nbsp; Everything in my C executes, so it seems like the hardware I built does not have errors in it, it just does not work.&nbsp; The VHDL is 2019 version:&nbsp;<a href="https://github.com/MATRIX7878/AXI4-I2C" rel="noopener noreferrer nofollow" target="_blank" data-e14adj="t">MATRIX7878/AXI4-I2C: A simple I2C for AXI4</a>.&nbsp; I have confirmed the sensor works by using the Avnet IIC temp sensor AXI4.</p> <p></p> <p>Thank you</p>https://community.element14.com/thread/233388?ContentTypeID=1Sun, 01 Feb 2026 22:16:39 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:46faea4d-0c07-4ad9-85e2-1d9d0ab0bbb3MATRIX78780https://community.element14.com/thread/233388?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>Interesting.&nbsp; Is the issue with how I am sending the data from PL to PS?&nbsp; I do not see an issue, but I am still learning AXI.&nbsp; No better way than to struggle, but this is ridiculous.</p><div style="clear:both;"></div>https://community.element14.com/thread/233373?ContentTypeID=1Sun, 01 Feb 2026 14:28:30 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:48f75fdd-6d9b-4a76-957f-c58ca1b57f4dveluv011https://community.element14.com/thread/233373?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>Probably there&#39;s an issue(at the state where it&#39;s reading the reg from temp module) with the I2C module in the VHDL.</p><div style="clear:both;"></div>https://community.element14.com/thread/233370?ContentTypeID=1Sun, 01 Feb 2026 04:13:02 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b207ae88-e93e-436e-b1c3-54fd297e7652jiedummy0https://community.element14.com/thread/233370?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/54111/openocd-working-with-zuboard-at-jtag-boot-mode/rss?ContentTypeId=0<p>Hi Muhbay,</p> <p>Sorry for the very very late reply.&nbsp;</p> <p>I can use FLYSWATTER FTDI probe to use OpenOCD with ARM in ZYNQMP.&nbsp; Only effort is making connector.&nbsp; The FLYSWATTER probe has voltage level translation on board.&nbsp; However, this way just for dealing with ARM of PS part in ZYNQMP, not the PL part.&nbsp;&nbsp;</p> <p>For programming FTDI bare chip EEPROM for making your own probe to work with ZYNQMP PL and PS parts, you can use FTDI EEPROM reading, writing tool.&nbsp; Reading EEPROM image from onboard FTDI chips of avnet boards, then write the image to the EEPROM of your bare FTDI boards.&nbsp; You will get the probes that can be used for both GCC/OpenOCD, and Vivado toolchains.&nbsp; I got the bare FTDI boards from FTDI directly.</p> <p>Best</p> <p>jiedummy</p><div style="clear:both;"></div>https://community.element14.com/thread/54111?ContentTypeID=0Wed, 13 Dec 2023 22:52:31 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:912e841b-f023-434f-afad-f095abb0157djiedummy11https://community.element14.com/thread/54111?ContentTypeID=0https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/54111/openocd-working-with-zuboard-at-jtag-boot-mode/rss?ContentTypeId=0<p>Did any one get openocd working with zuboard at jtag boot mode, sw2[1:4]={on|on|on|on}?<br />openocd version: v0.12.0</p>https://community.element14.com/thread/233369?ContentTypeID=1Sat, 31 Jan 2026 22:59:43 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7fba7da2-eeb3-43a1-8842-91184e489baaMATRIX78780https://community.element14.com/thread/233369?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>I use the IOBUF (tri-state) IP for the pins.&nbsp; I think I covered your point.&nbsp; If this is not what you meant, let me know please.</p><div style="clear:both;"></div>https://community.element14.com/thread/233368?ContentTypeID=1Sat, 31 Jan 2026 22:58:30 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:938ab767-7c55-4913-a558-f349caec90baMATRIX78781https://community.element14.com/thread/233368?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>2025.2 for both.&nbsp; Sure, here are the logs (I hope these are what you are looking for)</p> <p></p> <p>Syn:</p> <p><pre class="ui-code" data-mode="text"> *** Running vivado with args -log design_1_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl ****** Vivado v2025.2 (64-bit) **** SW Build 6299465 on Fri Nov 14 19:35:11 GMT 2025 **** IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 **** SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 **** Start of session at: Thu Jan 29 22:28:54 2026 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. source design_1_wrapper.tcl -notrace create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 534.707 ; gain = 221.895 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository &#39;c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0&#39;. WARNING: [IP_Flow 19-2207] Repository &#39;c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0&#39; already exists; ignoring attempt to add it again. INFO: [IP_Flow 19-1700] Loaded user IP repository &#39;c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0&#39;. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository &#39;C:/Xilinx/2025.2/Vivado/data/ip&#39;. add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 601.449 ; gain = 59.809 Command: read_checkpoint -auto_incremental -incremental C:/Users/matri/Documents/Temperature/Temperature.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/matri/Documents/Temperature/Temperature.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes Command: synth_design -top design_1_wrapper -part xczu1cg-sbva484-1-e Starting synth_design Attempting to get a license for feature &#39;Synthesis&#39; and/or device &#39;xczu1cg&#39; INFO: [Common 17-349] Got license for feature &#39;Synthesis&#39; and/or device &#39;xczu1cg&#39; INFO: [Device 21-403] Loading part xczu1cg-sbva484-1-e INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 12392 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1440.105 ; gain = 531.656 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module &#39;design_1_wrapper&#39; [C:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd:22] INFO: [Synth 8-3491] module &#39;design_1&#39; declared at &#39;c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:15&#39; bound to instance &#39;design_1_i&#39; of component &#39;design_1&#39; [C:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd:30] INFO: [Synth 8-638] synthesizing module &#39;design_1&#39; [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:26] INFO: [Synth 8-3491] module &#39;design_1_AXI4_I2C_0_0&#39; declared at &#39;C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_AXI4_I2C_0_0_stub.vhdl:6&#39; bound to instance &#39;AXI4_I2C_0&#39; of component &#39;design_1_AXI4_I2C_0_0&#39; [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:366] INFO: [Synth 8-638] synthesizing module &#39;design_1_AXI4_I2C_0_0&#39; [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_AXI4_I2C_0_0_stub.vhdl:39] INFO: [Synth 8-3491] module &#39;design_1_axi_smc_0&#39; declared at &#39;C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_axi_smc_0_stub.vhdl:6&#39; bound to instance &#39;axi_smc&#39; of component &#39;design_1_axi_smc_0&#39; [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:390] INFO: [Synth 8-638] synthesizing module &#39;design_1_axi_smc_0&#39; [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_axi_smc_0_stub.vhdl:117] INFO: [Synth 8-3491] module &#39;design_1_rst_ps8_0_100M_0&#39; declared at &#39;C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_rst_ps8_0_100M_0_stub.vhdl:6&#39; bound to instance &#39;rst_ps8_0_100M&#39; of component &#39;design_1_rst_ps8_0_100M_0&#39; [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:492] INFO: [Synth 8-638] synthesizing module &#39;design_1_rst_ps8_0_100M_0&#39; [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_rst_ps8_0_100M_0_stub.vhdl:28] INFO: [Synth 8-3491] module &#39;design_1_zynq_ultra_ps_e_0_0&#39; declared at &#39;C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_zynq_ultra_ps_e_0_0_stub.vhdl:6&#39; bound to instance &#39;zynq_ultra_ps_e_0&#39; of component &#39;design_1_zynq_ultra_ps_e_0_0&#39; [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:505] INFO: [Synth 8-638] synthesizing module &#39;design_1_zynq_ultra_ps_e_0_0&#39; [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/.Xil/Vivado-25556-DESKTOP-8DEH7IS/realtime/design_1_zynq_ultra_ps_e_0_0_stub.vhdl:100] INFO: [Synth 8-256] done synthesizing module &#39;design_1&#39; (0#1) [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/synth/design_1.vhd:26] INFO: [Synth 8-256] done synthesizing module &#39;design_1_wrapper&#39; (0#1) [C:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd:22] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1569.441 ; gain = 660.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1569.441 ; gain = 660.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1569.441 ; gain = 660.992 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1569.441 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0_in_context.xdc] for cell &#39;design_1_i/zynq_ultra_ps_e_0&#39; create_clock: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1569.441 ; gain = 0.000 Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0_in_context.xdc] for cell &#39;design_1_i/zynq_ultra_ps_e_0&#39; Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_AXI4_I2C_0_0/design_1_AXI4_I2C_0_0/design_1_AXI4_I2C_0_0_in_context.xdc] for cell &#39;design_1_i/AXI4_I2C_0&#39; Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_AXI4_I2C_0_0/design_1_AXI4_I2C_0_0/design_1_AXI4_I2C_0_0_in_context.xdc] for cell &#39;design_1_i/AXI4_I2C_0&#39; Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/design_1_axi_smc_0/design_1_axi_smc_0_in_context.xdc] for cell &#39;design_1_i/axi_smc&#39; Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/design_1_axi_smc_0/design_1_axi_smc_0_in_context.xdc] for cell &#39;design_1_i/axi_smc&#39; Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_in_context.xdc] for cell &#39;design_1_i/rst_ps8_0_100M&#39; Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_in_context.xdc] for cell &#39;design_1_i/rst_ps8_0_100M&#39; Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.srcs/constrs_1/new/temperature.xdc] Finished Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.srcs/constrs_1/new/temperature.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/matri/Documents/Temperature/Temperature.srcs/constrs_1/new/temperature.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1569.441 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1569.441 ; gain = 0.000 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1569.441 ; gain = 660.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xczu1cg-sbva484-1-e INFO: [Synth 8-6742] Reading net delay rules and data --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1569.441 ; gain = 660.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying &#39;set_property&#39; XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying &#39;set_property&#39; XDC Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1569.441 ; gain = 660.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1569.441 ; gain = 660.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 216 (col length:72) BRAMs: 216 (col length: RAMB18 72 RAMB36 36) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 1569.441 ; gain = 660.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1874.188 ; gain = 965.738 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1874.734 ; gain = 966.285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1885.402 ; gain = 976.953 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+-----------------------------+----------+ | |BlackBox name |Instances | +------+-----------------------------+----------+ |1 |design_1_AXI4_I2C_0_0 | 1| |2 |design_1_axi_smc_0 | 1| |3 |design_1_rst_ps8_0_100M_0 | 1| |4 |design_1_zynq_ultra_ps_e_0_0 | 1| +------+-----------------------------+----------+ Report Cell Usage: +------+----------------------------------+------+ | |Cell |Count | +------+----------------------------------+------+ |1 |design_1_AXI4_I2C_0_0_bbox | 1| |2 |design_1_axi_smc_0_bbox | 1| |3 |design_1_rst_ps8_0_100M_0_bbox | 1| |4 |design_1_zynq_ultra_ps_e_0_0_bbox | 1| +------+----------------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2135.441 ; gain = 1226.992 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.441 ; gain = 1226.992 Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2135.441 ; gain = 1226.992 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 2135.441 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2141.988 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: a6f9a5e5 INFO: [Common 17-83] Releasing license: Synthesis 37 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:01:06 . Memory (MB): peak = 2147.445 ; gain = 1545.996 INFO: [Common 17-1381] The checkpoint &#39;C:/Users/matri/Documents/Temperature/Temperature.runs/synth_1/design_1_wrapper.dcp&#39; has been generated. INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Thu Jan 29 22:30:20 2026... </pre></p> <p></p> <p>Impl:</p> <p></p> <p><pre class="ui-code" data-mode="text"> *** Running vivado with args -log design_1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace ****** Vivado v2025.2 (64-bit) **** SW Build 6299465 on Fri Nov 14 19:35:11 GMT 2025 **** IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 **** SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 **** Start of session at: Thu Jan 29 22:30:28 2026 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. source design_1_wrapper.tcl -notrace create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 529.961 ; gain = 218.285 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository &#39;c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0&#39;. WARNING: [IP_Flow 19-2207] Repository &#39;c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0&#39; already exists; ignoring attempt to add it again. INFO: [IP_Flow 19-1700] Loaded user IP repository &#39;c:/Users/matri/Documents/ip_repo/AXI4_I2C_1_0&#39;. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository &#39;C:/Xilinx/2025.2/Vivado/data/ip&#39;. add_files: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 616.723 ; gain = 76.750 Command: link_design -top design_1_wrapper -part xczu1cg-sbva484-1-e Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xczu1cg-sbva484-1-e INFO: [Project 1-5699] Read binary netlist with skipMacroContent - 1 INFO: [Project 1-454] Reading design checkpoint &#39;c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_AXI4_I2C_0_0/design_1_AXI4_I2C_0_0.dcp&#39; for cell &#39;design_1_i/AXI4_I2C_0&#39; INFO: [Project 1-454] Reading design checkpoint &#39;c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/design_1_axi_smc_0.dcp&#39; for cell &#39;design_1_i/axi_smc&#39; INFO: [Project 1-454] Reading design checkpoint &#39;c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0.dcp&#39; for cell &#39;design_1_i/rst_ps8_0_100M&#39; INFO: [Project 1-454] Reading design checkpoint &#39;c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.dcp&#39; for cell &#39;design_1_i/zynq_ultra_ps_e_0&#39; Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.812 . Memory (MB): peak = 963.578 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 30 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2025.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc] for cell &#39;design_1_i/zynq_ultra_ps_e_0/U0&#39; create_clock: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1092.113 ; gain = 39.152 Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc] for cell &#39;design_1_i/zynq_ultra_ps_e_0/U0&#39; Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0_board.xdc] for cell &#39;design_1_i/axi_smc/inst/clk_map/psr_aclk/U0&#39; Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0_board.xdc] for cell &#39;design_1_i/axi_smc/inst/clk_map/psr_aclk/U0&#39; Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/smartconnect.xdc] for cell &#39;design_1_i/axi_smc/inst&#39; Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_axi_smc_0/smartconnect.xdc] for cell &#39;design_1_i/axi_smc/inst&#39; Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_board.xdc] for cell &#39;design_1_i/rst_ps8_0_100M/U0&#39; Finished Parsing XDC File [c:/Users/matri/Documents/Temperature/Temperature.gen/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_board.xdc] for cell &#39;design_1_i/rst_ps8_0_100M/U0&#39; Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.srcs/constrs_1/new/temperature.xdc] Finished Parsing XDC File [C:/Users/matri/Documents/Temperature/Temperature.srcs/constrs_1/new/temperature.xdc] INFO: [Project 1-1714] 52 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1505.039 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 3 instances were transformed. IOBUF =&gt; IOBUF (IBUFCTRL, INBUF, OBUFT): 2 instances RAM16X1D =&gt; RAM32X1D (RAMD32(x2)): 1 instance 17 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 1505.039 ; gain = 888.316 Command: opt_design Attempting to get a license for feature &#39;Implementation&#39; and/or device &#39;xczu1cg&#39; INFO: [Common 17-349] Got license for feature &#39;Implementation&#39; and/or device &#39;xczu1cg&#39; Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1505.039 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 27e539b32 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.738 . Memory (MB): peak = 1505.039 ; gain = 0.000 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 27e539b32 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1948.418 ; gain = 0.000 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 27e539b32 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.042 . Memory (MB): peak = 1948.418 ; gain = 0.000 Phase 1 Initialization | Checksum: 27e539b32 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1948.418 ; gain = 0.000 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Detect if minReqCache needed Phase 2.1 Detect if minReqCache needed | Checksum: 27e539b32 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.079 . Memory (MB): peak = 1948.438 ; gain = 0.020 Phase 2.2 Timer Update Phase 2.2 Timer Update | Checksum: 27e539b32 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.274 . Memory (MB): peak = 1948.438 ; gain = 0.020 Phase 2.3 Timing Data Collection Phase 2.3 Timing Data Collection | Checksum: 27e539b32 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.293 . Memory (MB): peak = 1948.438 ; gain = 0.020 Phase 2 Timer Update And Timing Data Collection | Checksum: 27e539b32 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.295 . Memory (MB): peak = 1948.438 ; gain = 0.020 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-138] Pushed 57 inverter(s) to 204 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 20d95fedb Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.855 . Memory (MB): peak = 1948.438 ; gain = 0.020 Retarget | Checksum: 20d95fedb INFO: [Opt 31-389] Phase Retarget created 3 cells and removed 332 cells INFO: [Opt 31-1021] In phase Retarget, 80 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 269e3428b Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1948.438 ; gain = 0.020 Constant propagation | Checksum: 269e3428b INFO: [Opt 31-389] Phase Constant propagation created 2 cells and removed 166 cells INFO: [Opt 31-1021] In phase Constant propagation, 80 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1948.438 ; gain = 0.000 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1948.438 ; gain = 0.000 Phase 5 Sweep | Checksum: 1c026d34e Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1948.438 ; gain = 0.020 Sweep | Checksum: 1c026d34e INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 255 cells INFO: [Opt 31-1021] In phase Sweep, 101 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT. Phase 6 BUFG optimization | Checksum: 1c026d34e Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1948.438 ; gain = 0.020 BUFG optimization | Checksum: 1c026d34e INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1c026d34e Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020 Shift Register Optimization | Checksum: 1c026d34e INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 28ebd0d22 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020 Post Processing Netlist | Checksum: 28ebd0d22 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 95 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 343ba2d1a Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1948.438 ; gain = 0.000 Phase 9.2 Verifying Netlist Connectivity | Checksum: 343ba2d1a Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020 Phase 9 Finalization | Checksum: 343ba2d1a Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 3 | 332 | 80 | | Constant propagation | 2 | 166 | 80 | | Sweep | 0 | 255 | 101 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 95 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 343ba2d1a Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1948.438 ; gain = 0.020 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period &lt; 2.00 ns. Ending Power Optimization Task | Checksum: 343ba2d1a Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1948.438 ; gain = 0.000 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 343ba2d1a Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1948.438 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1948.438 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 43 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1948.438 ; gain = 443.398 INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1948.438 ; gain = 0.000 generate_parallel_reports: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1948.438 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1948.438 ; gain = 0.000 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1948.438 ; gain = 0.000 Writing XDEF routing. Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1948.438 ; gain = 0.000 Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1948.438 ; gain = 0.000 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1948.438 ; gain = 0.000 Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1948.438 ; gain = 0.000 Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1948.438 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint &#39;C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_opt.dcp&#39; has been generated. Command: place_design Attempting to get a license for feature &#39;Implementation&#39; and/or device &#39;xczu1cg&#39; INFO: [Common 17-349] Got license for feature &#39;Implementation&#39; and/or device &#39;xczu1cg&#39; INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1948.438 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 28ffbd739 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1948.438 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1948.438 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15d3d5733 Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 23d40066b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 23d40066b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 1 Placer Initialization | Checksum: 23d40066b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1.1 Partition Driven Placement Phase 2.1.1.1 PBP: Partition Driven Placement Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: 2084f9f02 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.1.1.2 PBP: Clock Region Placement INFO: [Place 30-3162] Check ILP status : ILP-based clock placer completed successfully. Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 1a95d1e38 Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.1.1.3 PBP: Compute Congestion Phase 2.1.1.3 PBP: Compute Congestion | Checksum: 1a95d1e38 Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.1.1.4 PBP: UpdateTiming Phase 2.1.1.4 PBP: UpdateTiming | Checksum: 1d3827a5e Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.1.1.5 PBP: Add part constraints Phase 2.1.1.5 PBP: Add part constraints | Checksum: 1d3827a5e Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.1.1 Partition Driven Placement | Checksum: 1d3827a5e Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.1 Floorplanning | Checksum: 19abb5652 Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 19abb5652 Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 19abb5652 Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 215cc67ff Time (s): cpu = 00:01:16 ; elapsed = 00:01:00 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 1dd473fad Time (s): cpu = 00:01:17 ; elapsed = 00:01:01 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 187 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 63 nets or LUTs. Breaked 0 LUT, combined 63 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-670] No setup violation found. Equivalent Driver Rewiring was not performed. INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 2530.645 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 63 | 63 | 0 | 1 | 00:00:02 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Equivalent Driver Rewiring | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 63 | 63 | 0 | 4 | 00:00:02 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1ef205fb5 Time (s): cpu = 00:01:26 ; elapsed = 00:01:11 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2.5 Global Place Phase2 | Checksum: 17c929250 Time (s): cpu = 00:01:40 ; elapsed = 00:01:20 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 2 Global Placement | Checksum: 17c929250 Time (s): cpu = 00:01:40 ; elapsed = 00:01:20 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1f3988dad Time (s): cpu = 00:01:54 ; elapsed = 00:01:30 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 3.2 Commit Most Macros &amp; LUTRAMs Phase 3.2 Commit Most Macros &amp; LUTRAMs | Checksum: 2172694aa Time (s): cpu = 00:01:54 ; elapsed = 00:01:30 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 3.3 Small Shape DP Phase 3.3.1 Small Shape Clustering Phase 3.3.1 Small Shape Clustering | Checksum: 1d3724e70 Time (s): cpu = 00:02:30 ; elapsed = 00:01:51 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 3.3.2 Slice Area Swap Phase 3.3.2.1 Slice Area Swap Initial Phase 3.3.2.1 Slice Area Swap Initial | Checksum: 1d838fd3b Time (s): cpu = 00:02:46 ; elapsed = 00:02:01 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 3.3.2 Slice Area Swap | Checksum: 1d838fd3b Time (s): cpu = 00:02:46 ; elapsed = 00:02:01 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 3.3 Small Shape DP | Checksum: 2070e2f90 Time (s): cpu = 00:03:11 ; elapsed = 00:02:16 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 3.4 Re-assign LUT pins Phase 3.4 Re-assign LUT pins | Checksum: 18306e4ed Time (s): cpu = 00:03:12 ; elapsed = 00:02:18 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 3.5 Pipeline Register Optimization Phase 3.5 Pipeline Register Optimization | Checksum: 18617b4d2 Time (s): cpu = 00:03:13 ; elapsed = 00:02:18 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 3 Detail Placement | Checksum: 18617b4d2 Time (s): cpu = 00:03:13 ; elapsed = 00:02:18 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1fdd64602 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=6.153 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1d8c5094f Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.117 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 258109ce4 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.153 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 4.1.1.1 BUFG Insertion | Checksum: 1fdd64602 Time (s): cpu = 00:03:26 ; elapsed = 00:02:28 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=6.153. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1aa88ec52 Time (s): cpu = 00:03:26 ; elapsed = 00:02:28 . Memory (MB): peak = 2530.645 ; gain = 582.207 Time (s): cpu = 00:03:26 ; elapsed = 00:02:28 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 4.1 Post Commit Optimization | Checksum: 1aa88ec52 Time (s): cpu = 00:03:26 ; elapsed = 00:02:28 . Memory (MB): peak = 2530.645 ; gain = 582.207 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 15da5b53e Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ________________________________________________________________________ | | Global Congestion | Long Congestion | Short Congestion | | Direction | Region Size | Region Size | Region Size | |___________|___________________|___________________|___________________| | North| 1x1| 1x1| 1x1| |___________|___________________|___________________|___________________| | South| 1x1| 1x1| 1x1| |___________|___________________|___________________|___________________| | East| 1x1| 1x1| 1x1| |___________|___________________|___________________|___________________| | West| 1x1| 1x1| 1x1| |___________|___________________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 15da5b53e Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 4.3 Placer Reporting | Checksum: 15da5b53e Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2530.645 ; gain = 0.000 Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207 Phase 4 Post Placement Optimization and Clean-Up | Checksum: bb98af65 Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207 Ending Placer Task | Checksum: b5620a16 Time (s): cpu = 00:03:40 ; elapsed = 00:02:39 . Memory (MB): peak = 2530.645 ; gain = 582.207 80 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:03:46 ; elapsed = 00:02:46 . Memory (MB): peak = 2530.645 ; gain = 582.207 INFO: [Vivado 12-24838] Running report commands &quot;report_control_sets, report_io, report_utilization&quot; in parallel. Running report generation with 2 threads. INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb INFO: [Vivado 12-24828] Executing command : report_io -file design_1_wrapper_io_placed.rpt report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.255 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote PlaceDB: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2530.645 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2530.645 ; gain = 0.000 Write Physdb Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint &#39;C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_placed.dcp&#39; has been generated. Command: phys_opt_design Attempting to get a license for feature &#39;Implementation&#39; and/or device &#39;xczu1cg&#39; INFO: [Common 17-349] Got license for feature &#39;Implementation&#39; and/or device &#39;xczu1cg&#39; Starting Initial Update Timing Task Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 6.157 | TNS= 0.000 | INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 91 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.554 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2530.645 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2530.645 ; gain = 0.000 Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.639 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint &#39;C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_physopt.dcp&#39; has been generated. Command: route_design Attempting to get a license for feature &#39;Implementation&#39; and/or device &#39;xczu1cg&#39; INFO: [Common 17-349] Got license for feature &#39;Implementation&#39; and/or device &#39;xczu1cg&#39; Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Phase 1 Build RT Design Checksum: PlaceDB: 21bacc65 ConstDB: 0 ShapeSum: 2975ae96 RouteDB: 6a318f1b Nodegraph reading from file. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.543 . Memory (MB): peak = 2530.645 ; gain = 0.000 Post Restoration Checksum: NetGraph: 141e6bef | NumContArr: a0546ec1 | Constraints: e7735333 | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 25e8f2880 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 25e8f2880 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 25e8f2880 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 2.3 Global Clock Net Routing Number of Nodes with overlaps = 0 Phase 2.3 Global Clock Net Routing | Checksum: 263d14f94 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 318cf0855 Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.306 | TNS=0.000 | WHS=-0.053 | THS=-0.757 | Phase 2.5 Soft Constraint Pins - Fast Budgeting Phase 2.5 Soft Constraint Pins - Fast Budgeting | Checksum: 284c59a07 Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2530.645 ; gain = 0.000 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 4475 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 3831 Number of Partially Routed Nets = 644 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 2b86b62da Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 2b86b62da Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 24c4ebf6e Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 4 Initial Routing | Checksum: 2339dd54b Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 611 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.978 | TNS=0.000 | WHS=-0.010 | THS=-0.010 | Phase 5.1 Global Iteration 0 | Checksum: 212aadfb4 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 5.2 Additional Iteration for Hold Phase 5.2 Additional Iteration for Hold | Checksum: 170e67ca5 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 5 Rip-up And Reroute | Checksum: 170e67ca5 Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.978 | TNS=0.000 | WHS=0.010 | THS=0.000 | INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.978 | TNS=0.000 | WHS=0.010 | THS=0.000 | Phase 6.1 Delay CleanUp | Checksum: 18852c711 Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 18852c711 Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 6 Delay and Skew Optimization | Checksum: 18852c711 Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.978 | TNS=0.000 | WHS=0.010 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 1abf4789c Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 7 Post Hold Fix | Checksum: 1abf4789c Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 1.08434 % Global Horizontal Routing Utilization = 1.03664 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 1abf4789c Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 1abf4789c Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 1abf4789c Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 11 Resolve XTalk Phase 11 Resolve XTalk | Checksum: 1abf4789c Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 12 Post Process Routing Phase 12 Post Process Routing | Checksum: 1abf4789c Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000 Phase 13 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=5.978 | TNS=0.000 | WHS=0.010 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 13 Post Router Timing | Checksum: 1abf4789c Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000 Total Elapsed time in route_design: 16.677 secs Phase 14 Post-Route Event Processing Phase 14 Post-Route Event Processing | Checksum: fe3459f3 Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: fe3459f3 Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 104 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Vivado 12-24828] Executing command : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt. report_methodology completed successfully INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Temperature grade: E, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Vivado 12-24838] Running report commands &quot;report_incremental_reuse, report_route_status&quot; in parallel. Running report generation with 2 threads. INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [Vivado 12-24828] Executing command : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb INFO: [Vivado 12-24828] Executing command : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation 121 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Temperature grade: E, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs generate_parallel_reports: Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.551 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2530.645 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 2530.645 ; gain = 0.000 Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2530.645 ; gain = 0.000 Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.726 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint &#39;C:/Users/matri/Documents/Temperature/Temperature.runs/impl_1/design_1_wrapper_routed.dcp&#39; has been generated. INFO: [Memdata 28-167] Found XPM memory block design_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[0].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the design_1_i/axi_smc/inst/switchboards/i_nodes/i_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[0].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block. Command: write_bitstream -force design_1_wrapper.bit Attempting to get a license for feature &#39;Implementation&#39; and/or device &#39;xczu1cg&#39; INFO: [Common 17-349] Got license for feature &#39;Implementation&#39; and/or device &#39;xczu1cg&#39; Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado 12-3199] DRC finished with 0 Errors INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Integrating Hard IP ELF/MEM with the PDI. INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design_1_wrapper.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Common 17-83] Releasing license: Implementation 136 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2530.645 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Thu Jan 29 22:36:12 2026... </pre></p><div style="clear:both;"></div>https://community.element14.com/thread/233366?ContentTypeID=1Sat, 31 Jan 2026 15:27:26 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:a9d0a8b7-c328-4ecc-b8b5-3eb55613b837embeddedguy0https://community.element14.com/thread/233366?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>Ok. That way, I will end up using the I2C of the PS itself. Just extended to PL pin for some reason but should be possible to use the I2C created on the PL entirely. That would be interesting to see.!</p><div style="clear:both;"></div>https://community.element14.com/thread/233363?ContentTypeID=1Sat, 31 Jan 2026 11:46:20 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:57cffeef-fec0-4aa8-ac4e-035eaabc281ajc20481https://community.element14.com/thread/233363?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>This might not be anything to do with the problem you&#39;re having, but I&#39;ll throw it in anyway for good measure.</p> <p>I have no direct experience with the Xilinx design software, but a problem that has come up here before a couple of times is to do with implementing tristates on the IO pins (you&#39;re using the tristate capability of the IO pins to emulate the open drain that you need for the I2C clock and data).</p> <p>As I understood it, the top level in your &#39;design block&#39; isn&#39;t the device pins, it&#39;s one layer down from the pins. It gets extended up to the pin level automatically when the system generates that intermediate layer for itself, on a one-to-one basis, but tristates need to be in a particular form, with signal(s) and enable, related together by naming. (If it wasn&#39;t done like that, the synthesis would mess things up by trying to give you the equivalent of an internal tristate bus between the layers and then optimising it out because it doesn&#39;t do anything.)</p> <p>It&#39;s possible that process may have changed in the time since those questions came up - as I say I don&#39;t use the design software, so wouldn&#39;t know - but it might be worth a quick look at how other people do this when writing for that platform.</p><div style="clear:both;"></div>https://community.element14.com/thread/233361?ContentTypeID=1Sat, 31 Jan 2026 09:27:02 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:45edecbf-1be6-455c-97b2-31027e8fa6d9veluv011https://community.element14.com/thread/233361?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>Which version of the Vivado and Vitis are you using? Can you share the syn and impl logs ?&nbsp;</p><div style="clear:both;"></div>https://community.element14.com/thread/233359?ContentTypeID=1Sat, 31 Jan 2026 09:19:10 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:c28482ec-feb2-430f-9f1c-55871e37fc6aMATRIX78780https://community.element14.com/thread/233359?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>I am using my I2C protocol so I can take advantage of the PL and PS combo and it is a great way (for me) to learn and see first-hand how the communication works.&nbsp; I tested the IIC AXI for the onboard temp sensor and it works, but when I use my AXI4 I made, I see my lines are stuck low or just sending noise.&nbsp; My variable in my C file is 0x00.&nbsp; As it is I2C, I would expect a line of 0xFF if the bus failed.&nbsp; I do not think I am communicating from the PL to the PS correctly.</p><div style="clear:both;"></div>https://community.element14.com/thread/233358?ContentTypeID=1Sat, 31 Jan 2026 09:15:26 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:50baa78e-18d6-4da5-8679-c859a6731616MATRIX78780https://community.element14.com/thread/233358?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>I normally do simulate, but I do not know how to simulate AXI with the PS.&nbsp; I looked at the AXI VIP, but do not know SystemVerilog and cannot find a good tutorial for custom IP blocks.&nbsp; I have tried an ILA before, but it never runs after I program the board in Vitis.&nbsp; Is there a more thorough guide out there that I haven&#39;t found despite searching all over the internet?&nbsp; I use VHDL as that is what I was trained in and prefer anyways to Verilog.</p><div style="clear:both;"></div>https://community.element14.com/thread/233357?ContentTypeID=1Sat, 31 Jan 2026 09:12:19 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f72e8d4a-1fed-433f-b058-d40e10610447MATRIX78780https://community.element14.com/thread/233357?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>With Vivado 2025.2, the AXI4 creator is bugged.&nbsp; At least that is what I have been told and what I have seen when I tried it myself.&nbsp; The thrill of building my own I2C (which I already have for pure FPGA logic) is higher than just using the standard AXI_IIC core for the temp sensor.&nbsp; Is it working correctly?</p><div style="clear:both;"></div>https://community.element14.com/thread/233354?ContentTypeID=1Sat, 31 Jan 2026 05:09:34 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:488d9299-edf7-457c-a29d-2c9b8023e916iksevas2https://community.element14.com/thread/233354?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>All you have to do is add the AXI I2C to your block design in Vivado (mapped to the I2C interface that you are targeting). Import the design XSA into Vitis and create a new platform based on the XSA. Then navigate in Vitis to the drivers that get created based on your XSA within the BSP. Find the AXI I2C driver and look all the way to the right in the driver window. You will see an option to IMPORT EXAMPLE designs. Pick the example design with best fits your targeted application. Hope this helps.</p><div style="clear:both;"></div>https://community.element14.com/thread/233353?ContentTypeID=1Sat, 31 Jan 2026 04:44:07 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:efadce67-123b-4119-a08f-00ed9f1d072bembeddedguy1https://community.element14.com/thread/233353?ContentTypeID=1https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56626/custom-axi4-lite-i2c-checking/rss?ContentTypeId=0<p>Is there any example for AXI I2C ? I want to try that too.&nbsp;</p><div style="clear:both;"></div>