• Ultra96V2 suddenly stop working

    Hi, I was running some examples on my Ultra96-V2 and it stopped working suddenly.

    No LEDs, no nothing.


    Any suggestions on where to start?

    The power supply looks OK, but when connected it goes down - maybe a short circuit somewhere in the board?


    Does the Ultra96…

  • Once and for all: WiFi on the Ultra96-v2 in a custom Petalinux build (please help)


    I represent a research group at University of Southern Denmark. We want to use the Ultra96-v2 for our work. Now we're at a point where we want to integrate our hardware design with high level software. Therefore, we are trying to run Ubuntu 20 on top…

  • Script make_u96v2_sbc_base.sh of version 2020.2 outputs error


    I am trying to run the 2020.2 make command based on https://github.com/Avnet/petalinux/blob/2020.2/scripts/make_u96v2_sbc_base.sh  .
    I have included bdf in Vivado by copy pasting them. I have checkout hdl and petalinux projects to version 2020.2 …

  • Ultra96v2 Wi-Fi certification

    Hello everyone,


    We have developed end product in which we are using Ultra96v2 board. Currently we are trying to certificate our product. In order to complete Wi-Fi tests in lab we need to be able to set Ultra96v2 Wi-Fi module (ATWILC3000) in TX only mode…

  • Issue of launching QEMU software emulation in Vitis



    I am new to ultra96v2 and the Vitis design suite. Currently, I am trying to run the vector addition example provided by Vitis. Everything works fine, until software emulation, the progress bar gets stuck on the "Waiting for the Linux TCF agent to start…

  • Pynq-overlay with custom xclbin



    We have purchased the Ultra96v2 board and we are trying to use Pynq with our custom OpenCL kernel code implemented in VITIS (output of .xclbin)


    We have downloaded the latest PYNQ SD card image (v2.6). We have build the Ultra96v2 platform using…

  • How do I compile the TensorFlow2 weight file for the Ultra96v2 board?

    Hello everyone,


    I am trying to compile the TensorFlow 2 weight file for the Ultra96v2 board. I am following this tutorial: https://github.com/Xilinx/Vitis-AI-Tutorials/blob/master/Design_Tutorials/08-tf2_flow/README.md. In the compiling step, ZCU102 and…

  • How to develop C based HLS complex PL systems on ZU+?

    Is C based Vivado high level synthesis a viable option to develop complex PL systems on Zynq? Does it have many limitations versus VHDL or Verilog?

  • Does Ultra96-V2 come with any video acceleration engine like codec?

    Does Ultra96-V2 come with any video acceleration engine like codec?

  • Current supported host OS and version for Xilinx tools?

    I'm worried about installing OS/App upgrades in case Vitis/Vivado won't work but on the other hand I'm worried about not installing updates to miss on security or bug fixes!  Do you have any advice?  I'm using a VM so I could take a snapshot…

  • Best way to start learning designing with Zynq UltraScale+?

    How to start learning? Start from HW followed by SW? Any list of knowledge to be learn "sequentially'"? Is it a one man show, and how long would it take?

  • Build R5 and PSU binaries without Vitis?

    Is it possible to build R5 and PSU binaries without Vitis?

  • I2C master that can provide SCK up to 1MHz?

    Is it possible to implement an i2c master block in Ultra96 that can provide SCK up to 1MHz?

  • Using Ultra96-V2 for DNN tasks?

    How do I judge whether Ultra96-V2 is able to cope for a certain DNN task? For example detecting vehicle and tracking at an intersection.  How to estimate its fps?

  • How to validate/verify my Vivado & Vitis install?

    What steps can I follow to validate/verify that my Vivado & Vitis tools are installed correctly?

  • Do I have to have a board definition to do a design in Vivado?

    I am new to Vivado and the Ultra96-V2 board.  Do I have to have a board definition to create my design?

  • Do I need both Vivado and Vitis?

    I plan on creating a design to run on the Ultra96-V2 board.  Do I need both the Vivado and Vitis tools for this?  How much do the tools cost?

  • Hardware Export after Vitis-example gives an error on PFM.IRQ


    I am trying to create an application project on Vitis again and import it on PYNQ.

    So I created the application by using avnet's automated 2020.1 oob script, then imported to Vitis  (build complete succesffully just not running on device the …

  • Clock input extension board for Ultra96

    We needed clock inputs 2xSMA 1 PPS and 10 MHz 3.3V biased square wave over 50 ohm for our application. We did not find anything off the shelf so we designed a simple board with KiCAD.


    We thought others might also need this. Check it out https://lightside…

  • Vivado 2021.1 default location of board files?

    I've done something stupid.  In following a Xilinx tutorial for simulation, it was setting up a project using a specific board which for some reason I couldn't select.  When I went to the Vivado Store to install the board, it was already installed…

  • Documentation links in Vitis 2021.1 not working

    When I look at a BSP for a platform in Vitis, I can see a list of drivers, against which are entries for 'Documentation Link' and 'Import Example'.  There's also a 'Documentation' link for the Operating System (in my case, standalone 7…

  • Vitis vs Vivado install

    Hi , et al,


    When I installed Vivado I chose the 'Vivado' option rather than the Vitis option. It seems to have installed a bunch of Vitis components as well but I don't know if it will be ok for doing the courses. Do I uninstall and re-install…

  • Where can I find the default arch.json file for Ultra96-V2?



    Is there anywhere I could find an arch.json file for the Ultra96-V2 platform?

    I am running into some issues when doing inference with the platform and I need to find out If I'm using the correct one.

    I have not gonne into flow design to get a…

  • how many EMIOs can be redefined in  low speed 40-pin expansion connector


    I plan to design own mezzanine card that connect to 40pin expansion connector.  There will be 20 IOs defined and used by FPGA side in my design. I can find 12 HD_GPIOs that can be used freely according to the schematics.

    Regarding the left 8 IOs, can…

  • Data Transfer Directly to a Mass Storage Device through USB

    I am on a project that basically aims following;

    1. receiving 16 Bit-10MSPS ADC 16-Pin parallel output during 5 minutes of cycles,
    2. creating a document on each cycle, and gathering the digital data received during the cycle into this document, and tagging…