• Maximizing Vivado Efficiency with Board Awareness

    Element14 is hosting a webinar that will teach you how to create your own board definition that makes Vivado "board-aware" of your own custom board. Please join us live or watch the recording at your convenience! community.element14.com/...…

  • ZedBoard (rev. D) not detected by Vivado

    Hello,

    I'm having trouble connecting my ZedBoard (rev. D) to Vivado.

    It was already flashed, and I can see U-Boot/etc output over Tera Term, so I don't think there's a cable issue here.
    I have downloaded the Cypress driver and the USB is managed…

  • Issue with FIR Compiler V7.2 in RFSoC Design

    I have an RFSoC Design using Vivado 2020.2 where I have an data stream coming from the RFDC Block at 1536 M Sample Per Second (MSpS).  The fabric won't clock at this rate so the RFDC block gives me a 8 sample wide stream blocking at 192 MHz.  The stream…

  • PicoZed-7030 issues with 1Gbps throughput using PS ethernet

    Hello! I'm working with a PicoZed using a Zynq-7030 SoC, and am having issues with getting anywhere near 1Gbps ethernet speeds. I have the ENET0 enabled with the MDIO, and is using MIO pins 16-27 (52-53 for MDIO). Under "Clock Configuration" I've set…

  • Hardware Export after Vitis-example gives an error on PFM.IRQ

    Hello,

    I am trying to create an application project on Vitis again and import it on PYNQ.

    So I created the application by using avnet's automated 2020.1 oob script, then imported to Vitis  (build complete succesffully just not running on device the …

  • Zedboard Rev.E Board Definition Files

    Hello,

    I want to make a FPGA project with Vivado 2020.1 for a Zedboard Rev.E. The included Board Definition Files in Vivado 2020.1 are in version 1.3 and 1.4 for Zedboard Rev.D. There are no Board Definition Files for the Zedboard Rev.E. With the Board…

  • PicoZed board definition files for Vivado 2018

    Hello

     

    I have found PicoZed board definition files for older versions of Vivado and definition files for fmc carriers, but have been unable to make either work.

    I am working with a custom board with a PicoZed 7020 and I need the board definition files.

     

     

     

    S…

  • Microzed Loading Encrypted Bitstream

    Hello,

    I am attempting to load an encrypted bitstream onto my microzed board (xc7z020) using vivado hardware manager. I am using BRAM to store the key currently want to get this working before moving to EFUSE. However I am running into some problems,…

  • Error building OOB Design in ISE 14.4

    Hi

    I am trying to build the out-of-box design myself, so I can modify it.

    I tried to follow this guide, but cannot generate the bitstream using xilinx platform studio that came with ISE 14.4 (The version that was used in the guide). I get the following…

  • ultra96v2 and vivado ports

    I am absolute a noob to the FPGA and Xilinx tools,

     

    https://forums.xilinx.com/xlnx/attachments/xlnx/DSPTOOL/22433/1/design_1.pdf

     

    what are those UART0_rtsn UART0_txd and GPIO-sensors ports? how to add those ports manully?

     

    I cannot find any definitions of…