The Si5317-EVB provides a complete and simple evaluation of the functions, features, and performance of the Si5317. The Si5317 is a pin-controlled 1:1 jitter-attenuating clock for high-performance applications.

The Si5317 is based on Silicon Laboratories' 3rd- generation DSPLL® technology, which provides any-rate jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user programmable, providing jitter performance optimization at the application level.

The Si5317 accepts a single clock input ranging from 1 M Hz to 710 MHz and generates two equal frequency clock outputs ranging from 1 to 710 MHz. The clock frequency range and loop bandwidth are selectable from a simple look-up table. The Si5317-EVB has a differential clock input that is AC terminated to 50ohm and then AC-coupled to the Si5317. The two clock outputs are AC-coupled. The XA- XB reference is usually a 114.285 MHz crystal; but there are provisions for an external XA-XB reference (either differential or single-ended). The device status is available on a ribbon header and LEDs. Control pins are strapped using jumper headers for device configuration and various board options. The board can be powered using either external power supplies or from a PC's USB port. Refer to the Si5317 data sheet for technical details of the device.

Applications: Data converter clocking, Switches and routers, Wireless infrastructure, Medical instrumentation, Networking, SONET/SDH, Test and measurement