https://community.element14.com/products/devtools/element14 Design Center is an online destination dedicated to providing electronics engineers with a complete end to end design solution. Find your next development tool using industry-leading Search Functionality and Product Data Features, all in one placen-USTelligent Community 12https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/ultrazed-hardware-design/56923/ultrazed-som-issue/235472Fri, 08 May 2026 20:11:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:2acb7ecd-29c4-41aa-b1db-26aceecaab7eiksevasThe BSPs for various tools versions are posted on a Sharepoint site. the code base used to generate those BSPs are on Avnet GITHUB.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/ultrazed-hardware-design/56923/ultrazed-som-issue/235466Fri, 08 May 2026 18:16:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d956c1ff-6155-49fb-90eb-1a8b7f9208e0chasekimHello, iksevas, Can you please let me know you built in design file and BSP of the PetaLinux. I want to know the difference between the two hardware versions. As i know that two device is same FPGA core.... Thanks,https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/ultrazed-hardware-design/56923/ultrazed-som-issue/235454Thu, 07 May 2026 21:30:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:33fb1d7e-7513-4c3b-9149-a6bfd3d6c3e8iksevasAny chance you can measure the eMMC clock? I would be curious to see between the two SOMs if the clock is changing frequency during the boot process. as far as determining if there is a build difference between your boards, I would look closely at the eMMC devices on the two boards and check to see if those are different device somehow. Could be as time and device availability could result in changes. Typically, the factory programs QSPI and eMMC with Linux out of box image. Perhaps it would make sense to get that reprogrammed onto SOM and see how that functions.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/ultrazed-hardware-design/56923/ultrazed-som-issueThu, 07 May 2026 20:36:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f885bc53-1a81-433c-86e4-9fa0ab592e89chasekimHello, I have a problem for new purchased of UltraZed SOM about the MMC access error by FSBL and I2C-2 read error, seems to be slow booting time via EMMC. We already verified all functions by SOM-1, but the SOM-2 continues to have problems. PS) Our build environment is Vivado 2022.1 and PetaLinux 2022.1 and Avnet release BPS. SOM-1) Purchased few years ago Serial number 4000086 191 000010 SOM-2) New Purchased serial number DMS2351279-2508 US2SOM REV 3-02-05 Please let me know if you have any recommend this issue.avnet boardshttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-example/235374Tue, 05 May 2026 19:39:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:5919abd0-c4d1-4f2f-8b9d-b7bf35688204thillTim, I sent you a friend request so I can message you directly.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-example/235372Tue, 05 May 2026 19:18:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f2224c25-239c-4c0e-98ae-8b2666ec1029Tim5000Hi thill yeah that would be really interesting to see what you've got!https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-example/235371Tue, 05 May 2026 19:00:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:75a00a3b-44f1-4333-912a-8efa6b8e20e4thillHi there, I'm an Avnet FAE and I built an EDF platform for ZUBoard using Codex. I'm new to EDF so it's hard to judge the quality of the result myself but it does boot, and I have terminal access via screen, ssh, and can ping both directions. I'm still working on developing this build so if this work would be useful for you guys I'm happy to share.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56900/vivado-version-pcie-xdma-reference/235286Sat, 02 May 2026 22:50:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:56899a87-d804-44c4-a7e8-6738800b1647iksevasThere 8 are capacitors on the board that are changing values to support Gen 4.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56900/vivado-version-pcie-xdma-reference/235285Sat, 02 May 2026 22:46:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8d5a394c-cc42-4478-a54f-ac2c22b0dd27rogrooteThanks. Our application requires PCIe Gen4 x4 and DDR4 at maximum speed, so upgrading to revision 2 of the board is necessary.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56900/vivado-version-pcie-xdma-reference/235267Sat, 02 May 2026 03:12:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:764e1050-c752-4609-8d65-7be3d7ac6223iksevasFYI - there is an article that Adam Taylor wrote called Perfecting PCIe on AUBoard I believe which should get you started down the correct path.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56900/vivado-version-pcie-xdma-reference/235266Sat, 02 May 2026 03:11:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:3a638549-5c6d-4fdc-ad60-54353599da97iksevasI think you can retarget the XDMA reference design to any of the tools for the most part. two gotchas: 1) generating the PCIe IP requires you to generate GT lanes to target the AUBoard. This differs from the default settings which more than likely were set to a different board. There is a check box on the last page of the IP settings which allows you to override the default so your XDC will actually take effect. 2) Rev 1 of the AUBoard has wrong capacitance value on the PCIe interface to support Gen 4 properly. This is elder to be resolved with a Rev 2 boards available next month.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56900/vivado-version-pcie-xdma-referenceFri, 01 May 2026 11:10:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:9ab087c4-bc04-4f6d-b911-083b28b9c054rogrooteHi all, I am looking for a reference PCIe XDMA design (Vivado project + host driver). Does anyone have a link to a solid / proven PCIe project targeting the AUBoard 15P? In addition: Which Vivado version(s) would you recommend for this board and XDMA? Any known pitfalls or good practices for this specific platform are also welcome. Thanks in advance. Kind regardshttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56867/pcie-srns-mode/235128Thu, 23 Apr 2026 17:32:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:4af59b10-4d3f-4c86-88aa-2e53e1e6dccbscwestI had done previously. My orginal design was a common clock and then converted it to SRNS. I chnaged the clock to be sourced SFP+ clk and unslected enable slot clock confgiuration. I think that there could other issues within my system causing these errors.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235127Thu, 23 Apr 2026 17:19:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:230e3d28-d2a4-465f-9a5e-6e4811103f1diksevasYeshttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235126Thu, 23 Apr 2026 17:03:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d804faf7-ed53-4332-ad0a-529729aa9961thillI think I see what I missed, I thought I could only share clocks from one quad away, but it seems you can share clocks 2 quads away if under 16.375 Gb/s. I assume you shared the clock source from quad 224 to quad 226 in your SFP solution?https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235125Thu, 23 Apr 2026 16:24:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:58c70d45-c9e0-45f3-8f53-056419c75101iksevasThe SFP port has been tested at full line rates using the clock generator in the reference design. Not sure why you think you can’t use that clock.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235124Thu, 23 Apr 2026 16:13:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:84b82d88-9aff-4079-86bc-ae8f7e61e14ethillThat is generally the flow we tried but the write failed. Was the SFP+ Module on this board ever tested? How is the clock for this SFP+ port meant to be configured? It shares a quad with HDMI transceivers and only has access to the HDMI rx recovered clock, and the clock generated by U56. Any more detailed guidance on how to verify structural differences in the memory? Will that involve making modifications to how microblaze is writing to I2C?https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235123Thu, 23 Apr 2026 16:01:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:1d4e59bd-b265-496d-81bc-60669f1612c8iksevasThat eeprom is targeted for hdmi EDID data. I’m not certain if the clock generator can be configured from that device. I certainly haven’t tried it as it’s not a use case for us. Your logic sounds correct, whether it would work is another story. You need to verify structural differences in the memory as well as access differences particularly with reference to the clock generator I2C.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235122Thu, 23 Apr 2026 15:54:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:718c825e-5116-4c94-ac8e-67d91e7787a9thillThanks for the reply. This flow configures U58 EEPROM (24AA025T) for the U57 clock generator. We need to configure the U56 clock generator which uses the U37 EEPROM (M24C64-RDW6TP). SFP+ shares a quad with the HDMI transceivers, and so we must use the HDMI clock generated by U56. The second clock generator does not route to quad 226 where SFP+ is bonded. <== For any future readers, this is the misconception. Clocks can be shared from two quads away. "For this guide, we will focus specifically on configuring the second programmable clock source, U57, through its associated EEPROM (24AA025T). This EEPROM stores the configuration data that customizes the clock generator settings, which are then applied during power-up. The 8T49N241 clock generator is a programmable device that supports both single-ended and differential outputs. The configuration values for the EEPROM will be generated using the Timing Commander Tool from Renesas," So I think to adjust the example from targeting U58 24AA025T to U37 M24C64-RDW6TP . Is that right? So the flow would be: 1. Change I2C pins from A9/B9 to R22/R23 2. Use the same IDT commander tool to generate config data 3. Program the data via microblaze/I2C? These EEPROMs are sized differently, and it makes me think the U37 EEPROM has additional data stored in it fro the rest of the HDMI subsystem. Does this example design still apply to the clock generator U56?https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56867/pcie-srns-mode/235119Thu, 23 Apr 2026 14:43:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:2b7122cd-9227-447c-9712-bd8f3e5bd6a9iksevasReview the GT settings in your design. The GTs in the PCIe IP provide a default mapping that is different from the AUBoard GT mapping. The last tab in the PCIe IP has an override button that will allow you to set the appropriate pinout constraint to map to the AUBoard.