https://community.element14.com/products/devtools/element14 Design Center is an online destination dedicated to providing electronics engineers with a complete end to end design solution. Find your next development tool using industry-leading Search Functionality and Product Data Features, all in one placen-USTelligent Community 12https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56867/pcie-srns-mode/235128Thu, 23 Apr 2026 17:32:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:4af59b10-4d3f-4c86-88aa-2e53e1e6dccbscwestI had done previously. My orginal design was a common clock and then converted it to SRNS. I chnaged the clock to be sourced SFP+ clk and unslected enable slot clock confgiuration. I think that there could other issues within my system causing these errors.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235127Thu, 23 Apr 2026 17:19:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:230e3d28-d2a4-465f-9a5e-6e4811103f1diksevasYeshttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235126Thu, 23 Apr 2026 17:03:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d804faf7-ed53-4332-ad0a-529729aa9961thillI think I see what I missed, I thought I could only share clocks from one quad away, but it seems you can share clocks 2 quads away if under 16.375 Gb/s. I assume you shared the clock source from quad 224 to quad 226 in your SFP solution?https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235125Thu, 23 Apr 2026 16:24:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:58c70d45-c9e0-45f3-8f53-056419c75101iksevasThe SFP port has been tested at full line rates using the clock generator in the reference design. Not sure why you think you can’t use that clock.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235124Thu, 23 Apr 2026 16:13:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:84b82d88-9aff-4079-86bc-ae8f7e61e14ethillThat is generally the flow we tried but the write failed. Was the SFP+ Module on this board ever tested? How is the clock for this SFP+ port meant to be configured? It shares a quad with HDMI transceivers and only has access to the HDMI rx recovered clock, and the clock generated by U56. Any more detailed guidance on how to verify structural differences in the memory? Will that involve making modifications to how microblaze is writing to I2C?https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235123Thu, 23 Apr 2026 16:01:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:1d4e59bd-b265-496d-81bc-60669f1612c8iksevasThat eeprom is targeted for hdmi EDID data. I’m not certain if the clock generator can be configured from that device. I certainly haven’t tried it as it’s not a use case for us. Your logic sounds correct, whether it would work is another story. You need to verify structural differences in the memory as well as access differences particularly with reference to the clock generator I2C.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235122Thu, 23 Apr 2026 15:54:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:718c825e-5116-4c94-ac8e-67d91e7787a9thillThanks for the reply. This flow configures U58 EEPROM (24AA025T) for the U57 clock generator. We need to configure the U56 clock generator which uses the U37 EEPROM (M24C64-RDW6TP). SFP+ shares a quad with the HDMI transceivers, and so we must use the HDMI clock generated by U56. The second clock generator does not route to quad 226 where SFP+ is bonded. <== For any future readers, this is the misconception. Clocks can be shared from two quads away. "For this guide, we will focus specifically on configuring the second programmable clock source, U57, through its associated EEPROM (24AA025T). This EEPROM stores the configuration data that customizes the clock generator settings, which are then applied during power-up. The 8T49N241 clock generator is a programmable device that supports both single-ended and differential outputs. The configuration values for the EEPROM will be generated using the Timing Commander Tool from Renesas," So I think to adjust the example from targeting U58 24AA025T to U37 M24C64-RDW6TP . Is that right? So the flow would be: 1. Change I2C pins from A9/B9 to R22/R23 2. Use the same IDT commander tool to generate config data 3. Program the data via microblaze/I2C? These EEPROMs are sized differently, and it makes me think the U37 EEPROM has additional data stored in it fro the rest of the HDMI subsystem. Does this example design still apply to the clock generator U56?https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56867/pcie-srns-mode/235119Thu, 23 Apr 2026 14:43:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:2b7122cd-9227-447c-9712-bd8f3e5bd6a9iksevasReview the GT settings in your design. The GTs in the PCIe IP provide a default mapping that is different from the AUBoard GT mapping. The last tab in the PCIe IP has an override button that will allow you to set the appropriate pinout constraint to map to the AUBoard.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56867/pcie-srns-mode/235118Thu, 23 Apr 2026 14:39:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d90dcc31-01b9-4c78-8cd0-15ed437b79cbscwestCurrently testing it with PCIe Gen 2. I have measured the clock and the frequency is correct and the peak to peak is ~0.7V which also should be fine.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-config/235116Thu, 23 Apr 2026 07:31:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:6c6be177-f448-485b-9efb-276cf2f7f9ebiksevasTrevor - there is a reference design on the website for the clock generator. https://www.avnet.com/wcm/connect/85941556-1002-4b59-9fc6-7ef59e1df223/aub-15p-dk-clkgen-v1p0.zip?MOD=AJPERES&ContentCache=NONE&CACHE=NONE&CVID=pikNCkzhttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56867/pcie-srns-mode/235115Thu, 23 Apr 2026 07:28:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:535015ae-11d4-4b64-ab5f-067211b7a852iksevasWhat date rates are you targeting? PCIe Gen 3 or earlier or PCIe Gen 4? The decoupling.caps on rev 1 for the board are not proper values for Gen 4 and linking with certain machines could prove troublesome. Also, have you been able to probe the 100MHz clock you generated to see how it looks?https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56872/auboard-15p-sfp-clock-configWed, 22 Apr 2026 21:14:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:ad627b09-9e60-477b-abef-65d7ab90ef40thillHello, I'm an AMD dedicated FAE at Avnet. My customer recently purchased AUBoard 15P to begin prototyping an SFP+ solution. It appears that the 10G SFP+ clock needs to come from component U56. Quick summary of what I have figured out so far: U56 = Renesas 8T49N241-998NLGI U56 provides clock to quad 226 MGTREFCLK0 (HDMI_CLK_8T49N241_N/P) U56 has an I2C interface accessible by pins R22 (SDA) and R23 (SCL) U56 expects RST pin connected to G22 to be driven HIGH to be enabled Is there a bring up and register write sequence we need to apply to U56 via the I2C connection to enable pass through instead of clock recovery, and program it to 156.25MHz for the SFP+ Module? Customer attempted to enable U56 by driving G22 reset pin high but did not see an output. Is the EEPROM available to the HDMI subsystem (U37) already programmed? They did attempt to apply the clock configuration example design that configures U57 EEPROM to U37 by changing the I2C pinout from B9/A9 (U57/U58 I2C bus) to R22/R23 (HDMI I2C bus) and running the IDT Timing Commander Tool -> EEPROM configuration tool, hopefully this attempted write did not cause U37 EEPROM to become misconfigured. Is there a way to verify U37 is correctly programmed? Are there any example designs available for this board that use the SFP+ module on quad 226? Thanks! TrevorAUBoard-15Psfp+renesashttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56867/pcie-srns-modeMon, 20 Apr 2026 15:06:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:605429d7-d7d7-42e1-9744-8b9a0992e8efscwestI have been trying to test pcie with asynchronus clocks. I have used the tutorial on programmable clock sources to update SFP+ clock to be 100MHz and used it as pcie ref clock. I have been having toruble establishing a link. I wanted to know if the termiantion on the SFP+ clk line would cuase any issues. There could be other factors like incresed loss in the set up cuasing this error, but I just wanted to make sure this was a viable path.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56461/how-to-enable-the-pg_c2m-power-good-to-mezzanine-signal-on-the-auboard-15p/235027Sun, 19 Apr 2026 02:09:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:0e7bb38e-5c21-459f-b477-92558c88decdvadimvOn the board I have, ALL of these components are not populated, or labeled... They are positioned in the same place as one of your layout screenshots above. I'll try to get an FMC interposer to pull up FMC D1 externally until the new rev goes for sale in June.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56461/how-to-enable-the-pg_c2m-power-good-to-mezzanine-signal-on-the-auboard-15p/235026Sun, 19 Apr 2026 01:29:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8a32506d-7d92-4d5e-bf6d-2084fa87ecd6iksevasSpec is probably best but I am willing to bet that either value would work. I would remove the pull down leg though as well, R603.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56461/how-to-enable-the-pg_c2m-power-good-to-mezzanine-signal-on-the-auboard-15p/235024Sun, 19 Apr 2026 00:52:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:e988097b-4de1-48b4-a0a7-0cb20646b38bvadimvIn the FMC spec this is supposed to be a 10k resistor pull-up. Is that an appropriate value, or should a stronger pull-up (like the 1k from above) be applied here?https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56461/how-to-enable-the-pg_c2m-power-good-to-mezzanine-signal-on-the-auboard-15p/235018Sat, 18 Apr 2026 22:58:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:41715f05-9635-4082-ac64-aa9206ab1dediksevasUnfortunately there is not a routed control to a GPIO pin here. I did send a note to the manufacturing team to update the BOM to place the DNP pull-up on PG_C2M for revision2 boards that are due out in June.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56461/how-to-enable-the-pg_c2m-power-good-to-mezzanine-signal-on-the-auboard-15p/235017Sat, 18 Apr 2026 22:41:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:63820055-f010-4bf4-9581-941ec15b0c68vadimvHi iksevas , Thank you for the schematic snippet. I see that I can install a 100k pull-up on R226 and generate the PG_C2M signal that my FMC card needs. Is the PG_C2M signal connected to an FPGA pin, and can it be driven? That would allow the FET to light the LED as an indicator without soldering... The FMC spec requires this signal to come from the carrier card (AU15P) to the FMC connector, so as currently implemented with Q9, it needs to be driven by something... Thanks for your help!https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-example/234479Wed, 18 Mar 2026 21:02:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:6c0ff19b-8627-4a92-9fe8-8ac179579db7iksevasUnfortunately, we have not extended the support for the ZUBoard to 2025.2 yet and we have not attempted to work within the new AMD EDF process. The last support for meta-avnet is 2024.2 which should be translatable/importable to 2025.2 using the older flow.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-exampleMon, 16 Mar 2026 17:50:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f54104f3-0e4c-40da-bcb7-c11b0a66c3e9Tim5000Hi has anyone tried to build linux/uboot for the 1CG using the 2025.2 AMD EDF? I've recently had an opportunity to dig my board out again and I'm trying to run it using the latest toolchains as petalinux is being deprecated. My previous toying with this were simple ones based on the Adam Taylor ones back in 2023 using petalinux loaded via tftpboot. I've regenerated the XSA and Vitis artifacts using the 2025.2 Vivado and Vitis applications but trying to get a successful Linux/u-boot build via AMD EDF v2025.2 seems to be eluding me. Generating the SDT from the XSA appears to go OK but building eventually fails - it seems many things are trying to be built that aren't needed e.g.(mali GPU) so I've ended up with a lot of things modified in my local.conf and still no success which makes me think it's not correctly targetting the board. meta-avnet doesn't appear to be updated for some time.ZU Board 1CGedf