https://community.element14.com/products/devtools/element14 Design Center is an online destination dedicated to providing electronics engineers with a complete end to end design solution. Find your next development tool using industry-leading Search Functionality and Product Data Features, all in one placen-USTelligent Community 12https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-example/234479Wed, 18 Mar 2026 21:02:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:6c0ff19b-8627-4a92-9fe8-8ac179579db7iksevasUnfortunately, we have not extended the support for the ZUBoard to 2025.2 yet and we have not attempted to work within the new AMD EDF process. The last support for meta-avnet is 2024.2 which should be translatable/importable to 2025.2 using the older flow.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56766/zuboard-1cg---amd-edf-2025-2-build-exampleMon, 16 Mar 2026 17:50:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:f54104f3-0e4c-40da-bcb7-c11b0a66c3e9Tim5000Hi has anyone tried to build linux/uboot for the 1CG using the 2025.2 AMD EDF? I've recently had an opportunity to dig my board out again and I'm trying to run it using the latest toolchains as petalinux is being deprecated. My previous toying with this were simple ones based on the Adam Taylor ones back in 2023 using petalinux loaded via tftpboot. I've regenerated the XSA and Vitis artifacts using the 2025.2 Vivado and Vitis applications but trying to get a successful Linux/u-boot build via AMD EDF v2025.2 seems to be eluding me. Generating the SDT from the XSA appears to go OK but building eventually fails - it seems many things are trying to be built that aren't needed e.g.(mali GPU) so I've ended up with a lot of things modified in my local.conf and still no success which makes me think it's not correctly targetting the board. meta-avnet doesn't appear to be updated for some time.ZU Board 1CGedfhttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56275/zub1cg---xdc-file/234447Mon, 16 Mar 2026 16:34:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b29604dd-8914-4171-bcf5-d8d8aa5b32ecsalasidisAs I said, I am new to this, so it would be nice if I could have an example application as a starting point. Is it possible to have one that uses the port with an if the shelf product (an ADC using syzygy)? If not at least show me how to define done if the lvds pins and the plain io pins, and I can do the rest. Thankshttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56275/zub1cg---xdc-file/234446Mon, 16 Mar 2026 16:25:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:178a695a-0ac7-41c3-8430-9518433fca23iksevasUnfortunately, the HSIO interface is generic so adding something to the BDF which could be defined as any interface that fits the expansion connector isn't a proper setting. If you have a module identified to use with the expansion connector, I suggest you then implement the interface needed for that particular interface in the block design standalone. You will either need to implement either your own IP or IP specific to the interface, ie - I2C, SPI, etc. You will also need to map those interfaces to external pins and provide constraints to implement it properly. The schematic for this board is available so any IO not presented in the BDF can be mapped to an XDC file.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56760/oob---qc-test-not-passed/234444Mon, 16 Mar 2026 12:38:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:5af860fa-05f6-4def-89eb-daae2176545ciulyanovHi iksevas, Thank you. With this file everything worked as expected out-of-the-box. The server started successfully. So, fortunately, my FMC did not damage the carrier. It would indeed be good to update the online link to the working OOB version. Thanks again for your attention, the issue is now resolved.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/zuboard/56275/zub1cg---xdc-file/234419Sat, 14 Mar 2026 20:19:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:424f1b3a-ec45-4ecc-86ab-f58e6333712csalasidisThe project was on a back burner for a while. Is there an example application of how to create the xdc pin mappings for the SYZYGY ports, and how to use them. I have found no example projects, or any definitions. The Board BDF file that is installed in Vivado only has some serial interfaces, buttons and LEDs defined, and not much else. New to using this, so sorry if the solution is obvioushttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56760/oob---qc-test-not-passed/234409Fri, 13 Mar 2026 18:47:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:841b56b4-4c4f-49b8-bf3a-709b5ae041eciksevasHere is an OOB MCS file that you should be able to program. I will have the team update the MCS file online. Let me know if this works for you. community.element14.com/.../au15p_5F00_oob.ziphttps://community.element14.com/products/devtools/avnetboardscommunity/azure-sphere-starter-kits/f/forum/56736/azure-sphere-starter-kit-availability/234380Thu, 12 Mar 2026 23:01:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:bd436cdf-77ef-423c-bee2-32699eef72ediksevashttps://www.avnet.com/americas/products/avnet-boards/avnet-board-families/ms-azure-sphere/ Looking on this page it appears discontinued.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56760/oob---qc-test-not-passed/234379Thu, 12 Mar 2026 22:54:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:603004a2-34c1-43fb-bcb0-2bf6424bb475iksevasI believe there is a software check that requires the QC Test to pass before programming the Out of box. You won’t be able to pass that test without test equipment. II’ll get back to you after done review to see if you gave option to program OOB mcs without factory test.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/ultra96-hardware-design/56761/ultra96v2-xadc-ip-not-loading-on-vivadoThu, 12 Mar 2026 09:25:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d12a1c1b-50cf-43b0-b3c9-20f8085c3c95DelronHello I am handling a project based on Zynq + MPSoC on the Ultra96v2 and l want to use the PL with the PS .However l cannaot seem to add the XADC IP layer on Vivado to build the hardware implementation.Is there any possible work around to get the system working?Also any possible workflows on using Yocto development guides that could make things simpler for me? Thank you for your assistanceask_an_expertfpgaask_the_expertlinuxhttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/auboard-15p/56760/oob---qc-test-not-passedWed, 11 Mar 2026 16:44:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:2eda8c65-92d4-4e32-9b18-49aa6100c2b8iulyanovHello, I am working with the AUBoard-15P carrier together with my own custom FMC card. Earlier, my FMC card had a hardware issue that caused voltage drops on the AUBoard 3.3 V rail. I have now removed the FMC card and I am trying to restore the board to a known-good state by reflashing the official Out-of-Box image to the on-board QSPI flash. I used the OOB package from: http://avnet.me/auboard-15p-dk-oob and programmed the provided au15p_firmware.mcs into QSPI using Vivado Hardware Manager. After reflashing, the board no longer starts the web-server demo. Instead, the UART log shows: AU15P Board SPI Flash Bootloader v1.0 Build on Oct 15 2024 INFO: QC test not passed, launch QC test program now. Boot application AU15P_TEST.elf .. XEMacLite detect_phy: PHY detected at address 1. auto-negotiated link speed: 100 The bootloader launches AU15P_TEST.elf instead of the expected OOB application / web server. So, my question is Is the QC/test application source code available , or at least a description of what it checks? I would like to identify whether the earlier FMC-related fault may have damaged some part of the carrier board. I have strong concerns about it. Maybe I am using an OOB image that is not appropriate for my board version, and the board itself is OK? My board is AUB-15P-DK-PCB-1 Any guidance would be appreciated. Thank you.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/ultrazed-hardware-design/56728/mechanical-drawing-for-the-aes-zu-pciecc-g/234184Wed, 04 Mar 2026 23:43:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:798fe71c-62b9-4118-baa1-612833f57b64iksevasThe FMC mechanicals are standard. Your FMC add-on card should follow standard outline / mounting holes. Checkout this page for some docs that may help: FMCHUB.COM – FPGA Mezzanine Cards (FMC)https://community.element14.com/products/devtools/avnetboardscommunity/azure-sphere-starter-kits/f/forum/56736/azure-sphere-starter-kit-availabilityWed, 04 Mar 2026 08:26:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:51855cf4-b36e-4fc7-a3cb-7ceef9180badkoe14Hi there, is there any plan to release an Azure Sphere Starter Kit v3 or is Azure Sphere development completely discontinued?https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/ultrazed-hardware-design/56728/mechanical-drawing-for-the-aes-zu-pciecc-gMon, 02 Mar 2026 07:47:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:298785a2-db83-4839-ad8e-fe9a42c46d3dP.BrogliI have found the pdf with the name: AES-ZU-PCIECC-G-Mechanical-v1.PDF ( AES-ZU-PCIECC-G-Mechanical-v1.PDF - element14 Community ) I want to design a card for the FMC connector need the dimensions for it, particularely the positions of the holes on the carrier card. And those are not given in that pdf. Is there a mechanical drawing that is more complete? Thank youultrazedAES-ZU-PCIECC-Gmechanical drawinghttps://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/rfsoc-hardware-design/56692/zcu208-2024b-and-2025a/234008Tue, 24 Feb 2026 19:28:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:233e0287-307d-4ba2-a68d-6695874334d4mbrownHello drew314 , Please try unchecking the "Generate Simulink Software Interface mdoel' box in step 4.2. If I recall correctly, the ADCCapture design is HDL-only.https://community.element14.com/products/devtools/avnetboardscommunity/avnetboard-forums/f/rfsoc-hardware-design/56692/zcu208-2024b-and-2025aThu, 19 Feb 2026 15:54:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d709214c-af9d-46ff-a5ba-f18aa38b92ccdrew314I am trying to generate HDL and SW project for ZCU208 IQ example. I have matlab 2024b and 2025a installed. Running though the HDL workflow advisor with unmodified slx, I get this error for both the Real and IQ examples. I get the error both in 2024b and 2025a. I have the IIO stream blocks in my simulink library, but do not know what to do with them. Note No driver block was generated for port(s) "Tile0 ADC Ch0 Data" mapped to interface "Tile0 ADC Ch0 Data" in the software interface model. Note No driver block was generated for port(s) "Tile0 ADC Ch0 Valid" mapped to interface "Tile0 ADC Ch0 Valid" in the software interface model. Note No driver block was generated for port(s) "Tile0 DAC Ch0 Data" mapped to interface "Tile0 DAC Ch0 Data" in the software interface model. Note No driver block was generated for port(s) "Tile0 DAC Ch0 Valid" mapped to interface "Tile0 DAC Ch0 Valid" in the software interface model. Warning The AXI4-Stream IIO driver block cannot be automatically generated in the software interface model when a scalar port, "MM2S_Data", is mapped to AXI4-Stream interface "AXI4-Stream DMA". Before you generate code from the software interface model, add the AXI4-Stream IIO driver block from "Simulink Library Browser" -> "Embedded Coder Support Package for AMD SoC Devices" library, change "MM2S_Data" into a vector, and connect the vector port to the driver block. Warning The AXI4-Stream IIO driver block cannot be automatically generated in the software interface model when a scalar port, "S2MM_Data", is mapped to AXI4-Stream interface "AXI4-Stream DMA". Before you generate code from the software interface model, add the AXI4-Stream IIO driver block from "Simulink Library Browser" -> "Embedded Coder Support Package for AMD SoC Devices" library, change "S2MM_Data" into a vector, and connect the vector port to the driver block. Note No driver was generated for port(s) "Tile0 ADC Ch0 Data" mapped to interface "Tile0 ADC Ch0 Data" in the host interface script. Note No driver was generated for port(s) "Tile0 ADC Ch0 Valid" mapped to interface "Tile0 ADC Ch0 Valid" in the host interface script. Note No driver was generated for port(s) "Tile0 DAC Ch0 Data" mapped to interface "Tile0 DAC Ch0 Data" in the host interface script. Note No driver was generated for port(s) "Tile0 DAC Ch0 Valid" mapped to interface "Tile0 DAC Ch0 Valid" in the host interface script. Failed Generate Software Interface. Generating new Zynq Software Interface model: gm_rfsocADCCapture_interface SoC Blockset and SoC Blockset Support Package for AMD FPGA and SoC Devices are required to generate software interface model. Zynq Software Interface model generation complete. Generating new Xilinx Host Interface script: gs_rfsocADCCapture_interface.m Xilinx Host Interface script generation complete.https://community.element14.com/products/devtools/f/forum/56690/another-critical-bug-in-openssl/233840Thu, 19 Feb 2026 12:00:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:56c7cdee-9b25-446d-b180-62b1acad5d10JWxbtw - I wanted to place this in "software" but couldn't find a mean to add something there, so I placed it one level uphttps://community.element14.com/products/devtools/f/forum/56690/another-critical-bug-in-openssl/233838Thu, 19 Feb 2026 11:38:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:629c6370-06e1-4d89-9e31-f0c71c3d1e6bJWxFortunately this one seems (for now) to not include TLS, which would render many SSL enabled devices in need of update...