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<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/"><channel><title>Altera Arria FPGA Series Overview</title><link>https://community.element14.com/products/devtools/technicallibrary/w/documents/10096/altera-arria-fpga-series-overview</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>Altera Arria FPGA Series Overview</title><link>https://community.element14.com/products/devtools/technicallibrary/w/documents/10096/altera-arria-fpga-series-overview</link><pubDate>Wed, 27 Jun 2012 00:23:58 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:6f86bcaf-bec3-4dc8-975b-adc065e1d824</guid><dc:creator>atomar</dc:creator><comments>https://community.element14.com/products/devtools/technicallibrary/w/documents/10096/altera-arria-fpga-series-overview#comments</comments><description>Current Revision posted to Documents by atomar on 6/27/2012 12:23:58 AM&lt;br /&gt;
&lt;div&gt; &lt;/div&gt;&lt;table border="0" cellpadding="3" cellspacing="0" class="jiveNoBorder" style="border:0px solid #000000;width:100%;"&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td style="border:0px solid black;border:0px solid #000000;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;text-align:left;color:#333333;"&gt;&lt;a href="/products/devtools/technicallibrary/w/documents/9958/altera-overview"&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/300x300/__key/communityserver-wikis-components-files/00-00-00-01-46/0131.contentimage_5F00_17988.png"&gt;&lt;img alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/0131.contentimage_17988.png-300x300.png?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=sQmJgmtV9Cs4%2BEBO1zCgmKxoleFuQqgeJQ8aoWekZsw%3D&amp;amp;se=2026-05-01T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=0xxM9V+0oQ3P0klT3jK8Qg==" style="max-height: 300px;max-width: 300px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/a&gt;&lt;/td&gt;&lt;td style="border:0px solid black;border:0px solid #000000;text-align:center;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;color:#333333;"&gt;&lt;strike style="text-align:right;"&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/300x300/__key/communityserver-wikis-components-files/00-00-00-01-46/1602.contentimage_5F00_17989.png"&gt;&lt;img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/1602.contentimage_17989.png-300x300.png?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=4GSCobFRm%2BRiBgrKx63Ir6XPt1ppbvtXjqE8EG5m6p8%3D&amp;amp;se=2026-05-01T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=WzhvIYclS0VAIw+sd/qu/g==" style="max-height: 300px;max-width: 300px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/strike&gt;&lt;/td&gt;&lt;td style="border:0px solid black;border:0px solid #000000;text-align:right;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;color:#333333;"&gt;&lt;a href="/products/devtools/technicallibrary/w/documents/9456/development-kit-line-card---altera"&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/300x300/__key/communityserver-wikis-components-files/00-00-00-01-46/0216.contentimage_5F00_17990.png"&gt;&lt;img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/0216.contentimage_17990.png-300x300.png?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=N9DpeqU%2F05PB428IP5QMCmg5QclMA3ahHyJQe759Igc%3D&amp;amp;se=2026-05-01T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=mDTQtb8mdt+yJ4pF8Q8Jig==" style="max-height: 300px;max-width: 300px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/a&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;hr /&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/150x36/__key/communityserver-wikis-components-files/00-00-00-01-46/6153.contentimage_5F00_17991.jpg"&gt;&lt;img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/6153.contentimage_17991.jpg-150x36.jpg?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=XpfeoMVGoftl9kkZELBaV5xOJrBWBRLiCV8d5mnjWsA%3D&amp;amp;se=2026-05-01T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=E7z6am5sD9AQfi7xflDuqQ==" style="max-height: 36px;max-width: 150px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/p&gt;&lt;h2&gt;&lt;strong&gt;Arria FPGA Series&lt;/strong&gt;&lt;/h2&gt;&lt;p style="margin:0;"&gt;&lt;strong&gt;&lt;br /&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;Altera&amp;#39;s Arria&lt;span class="emoticon" data-url="https://community.element14.com/cfs-file/__key/system/emoji/00ae.svg" title="Registered"&gt;&amp;#x00ae;&lt;/span&gt; FPGA series is designed for cost- and power-sensitive transceiver-based applications. The Arria FPGA series has a rich feature set of memory, logic, and digital signal processing (DSP) blocks combined with the superior signal integrity of up to 10G transceivers to allow you to integrate more functions and maximize system bandwidth. The Arria series includes Arria GX, Arria II, and Arria V devices with on-chip transceivers that allow the transfer of serial data in and out of the FPGA at high frequencies.The newest member to the Arria series is the Arria V FPGA with integrated 10G transceivers. Compare Arria series devices at our online Product Selector.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;table border="1" cellpadding="3" cellspacing="0" class="jiveBorder" style="border:1px solid #000000;width:80%;"&gt;&lt;thead&gt;&lt;tr&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;&lt;br /&gt;&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;Arria GX&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10085/altera-arria-ii-fpga-architecture-overview"&gt;&lt;span style="color:#ffffff;"&gt;Arria II&lt;/span&gt;&lt;/a&gt; GX&lt;br /&gt;&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10085/altera-arria-ii-fpga-architecture-overview"&gt;&lt;span style="color:#ffffff;"&gt;Arria II&lt;/span&gt;&lt;/a&gt; GZ&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10103/altera-arria-v-fpga-architecture-overview"&gt;&lt;span style="color:#ffffff;"&gt;Arria V&lt;/span&gt;&lt;/a&gt;&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td style="border:1px solid black;border:1px solid #000000;background-color:transparent;padding:3px;text-align:left;color:#000000;"&gt;Year of Introduction&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;2007&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;2009&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;2010&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;2011&lt;/td&gt;&lt;/tr&gt;&lt;tr&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:left;background-color:transparent;padding:3px;color:#000000;"&gt;Process Technology&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;90 nm&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;40 nm&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;40 nm&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;28 nm&lt;/td&gt;&lt;/tr&gt;&lt;tr&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:left;background-color:transparent;padding:3px;color:#000000;"&gt;Recommended for New Designs&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;Yes&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;Yes&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;Yes&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;Yes&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10103/altera-arria-v-fpga-architecture-overview"&gt;Arria V&lt;/a&gt; FPGA&lt;/strong&gt; - The Arria V FPGA family offers the lowest power and lowest system cost for mainstream applications. Arria V FPGAs include unique innovations such as the lowest power transceivers at 6G and 10G, a powerful collection of hard intellectual property (IP), and a power-optimized core architecture comprised of redesigned adaptive logic modules (ALMs), variable-precision DSP blocks, distributed and new M10K embedded memory blocks, and fractional clock synthesis phase-locked loops (PLLs). With these innovations, Arria V FPGAs deliver the power, bandwidth, and cost to meet your unique design needs. &lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10085/altera-arria-ii-fpga-architecture-overview"&gt;Arria II&lt;/a&gt; FPGA&lt;/strong&gt; - The Arria II FPGA family is ideal for cost-sensitive applications. Arria II FPGAs are based on a 40-nm, full-featured FPGA fabric that includes ALMs, DSP blocks, embedded RAM, and a hard PCI Express&lt;span class="emoticon" data-url="https://community.element14.com/cfs-file/__key/system/emoji/00ae.svg" title="Registered"&gt;&amp;#x00ae;&lt;/span&gt; IP core. The Arria II GX and GZ FPGAs from the Arria II FPGA family feature the industry&amp;#39;s lowest power FPGAs with up to 6.375-Gbps transceivers. Unlike other 6G FPGA families, Altera&amp;#39;s Arria II FPGA family offers improvements in usability that allow you to complete your projects faster.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;&lt;strong&gt;Arria GX FPGA&lt;/strong&gt; - The Arria GX FPGA family is Altera&amp;#39;s cost-optimized 90-nm FPGA family with transceivers. With transceiver speeds up to 3.125 Gbps, you can connect existing modules, devices, and support protocols such as PCI Express, Gbps Ethernet, Serial RapidIO&lt;span class="emoticon" data-url="https://community.element14.com/cfs-file/__key/system/emoji/00ae.svg" title="Registered"&gt;&amp;#x00ae;&lt;/span&gt;, SDI, XAUI, and more. The Arria GX FPGA family incorporates Altera’s proven transceiver technology, ensuring excellent signal integrity for your designs.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;text-align:right;"&gt;&lt;a class="jive-link-anchor-small" href="#top"&gt;Back to top&lt;/a&gt;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;hr /&gt;&lt;table border="0" cellpadding="3" cellspacing="0" class="jiveNoBorder" style="border:0px solid #000000;width:100%;"&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td style="border:0px solid black;border:0px solid #000000;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;text-align:left;color:#333333;"&gt;&lt;a href="/products/devtools/technicallibrary/w/documents/9958/altera-overview"&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/300x300/__key/communityserver-wikis-components-files/00-00-00-01-46/1205.contentimage_5F00_17992.png"&gt;&lt;img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/1205.contentimage_17992.png-300x300.png?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=xsWfC9gdcNHkamGU26zjU9oXwrSrKTKb8Wx1q5tn6Ew%3D&amp;amp;se=2026-05-01T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=0xxM9V+0oQ3P0klT3jK8Qg==" style="max-height: 300px;max-width: 300px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/a&gt;&lt;/td&gt;&lt;td style="border:0px solid black;border:0px solid #000000;text-align:center;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;color:#333333;"&gt;&lt;strike style="text-align:right;"&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/300x300/__key/communityserver-wikis-components-files/00-00-00-01-46/4747.contentimage_5F00_17993.png"&gt;&lt;img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/4747.contentimage_17993.png-300x300.png?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=Tf%2BorxTYKfYDA7npMqRpkODSTOCfvE6rt4iX1Ll8dic%3D&amp;amp;se=2026-05-01T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=WzhvIYclS0VAIw+sd/qu/g==" style="max-height: 300px;max-width: 300px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/strike&gt;&lt;/td&gt;&lt;td style="border:0px solid black;border:0px solid #000000;text-align:right;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;color:#333333;"&gt;&lt;a href="/products/devtools/technicallibrary/w/documents/9456/development-kit-line-card---altera"&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/300x300/__key/communityserver-wikis-components-files/00-00-00-01-46/3252.contentimage_5F00_17994.png"&gt;&lt;img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/3252.contentimage_17994.png-300x300.png?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=nloUEeAeZcrHjUvdA4pXK4TGMZUyu4XAwvRicPA4GKE%3D&amp;amp;se=2026-05-01T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=mDTQtb8mdt+yJ4pF8Q8Jig==" style="max-height: 300px;max-width: 300px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/a&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;hr /&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;

&lt;div style="font-size: 90%;"&gt;Tags: arria_gx, fpga, arria_v, arria_10, altera, arria, arria_ii&lt;/div&gt;
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