Altera Cyclone III FPGA Architecture Overview

atomar — Wed, 27 Jun 2012 00:25:24 GMT

Current Revision posted to Documents by atomar on 6/27/2012 12:25:24 AM

Cyclone III FPGA Architecture

Cyclone® III FPGAs offer an unprecedented combination of low power, high functionality, and low cost. The architecture consists of up to 120K vertically arranged logic elements (LEs), 4 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, and 200 18x18 embedded multipliers. Cyclone III LS FPGAs have a memory-rich and multiplier-rich floorplan consisting of up to 200K logic elements, 8.2 Mbits of embedded memory, and 396 embedded multipliers.

Both architectures include highly efficient interconnect and low-skew clock networks, providing connectivity between logic structures for clock and data signals. The logic and routing core fabric is surrounded by I/O elements (IOEs) and phase-locked loops (PLLs), as shown below

Key Features

Power
Density
Embedded 18 x 18 Multipliers
Embedded Memory
Cost-Optimized Architecture
Clock Management

Connectivity

External Memory Interfaces
I/O Flexibility
Interface and Protocol Support
Signal Integrity
On-Chip Termination

Altera adopted a new design methodology to ensure Cyclone III FPGAs would successfully meet low-cost goals for high-volume applications. The traditional "optimization-by-elimination" approach involves reducing the cost of an existing high-density product by eliminating features in software. Although this method is marginally effective in reducing FPGA cost, it does not attain the lowest possible price points for a given die size and package.

Cyclone III FPGAs take advantage of the benefits of 65-nm technology (small die size, high density and low cost) with up to three speed grades higher performance than competing low-cost FPGAs. Cyclone III FPGAs are pad limited. A pad-limited die means the I/O structure is as small as possible, and therefore the die cost is at its lowest. In addition, the Cyclone III FPGAs offer staggered I/O pads, meaning that two rows of I/O pads are interleaved, increasing the number of available I/O pads.

Cyclone III FPGAs were built starting with the careful selection of small form-factor packages that offer sufficient user I/O pins and the lowest-cost structure. From the physical dimensions of the package, the maximum size of a pad-limited die can be determined. The logic is then populated with as many logic elements (LEs), memory blocks, dedicated multipliers, and other customer-defined features as possible, guaranteeing the most functionality in the available area.

Tags: fpga, cyclone_iii, altera