Altera Cyclone IV FPGA Architecture Overview

atomar — Wed, 27 Jun 2012 00:24:57 GMT

Current Revision posted to Documents by atomar on 6/27/2012 12:24:57 AM

Cyclone IV FPGA Architecture

Cyclone® IV FPGAs continue the Cyclone series tradition of offering an unprecedented combination of low power, high functionality, and low cost. The Cyclone IV GX FPGA architecture consists of up to 150K vertically arranged logic elements (LEs), 6.5 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, and 360 18 x 18 embedded multipliers. New to the Cyclone series, Cyclone IV GX FPGAs feature integrated transceivers at up to 3.125 Gbps.

The Cyclone IV E FPGA architecture consists of up to 115K vertically arranged LEs, 4 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, and 266 18 x 18 embedded multipliers. The logic and routing core fabric is surrounded by I/O elements (IOEs) and phase-locked loops (PLLs), as shown in Figure 1. Both GX and E devices have four general-purpose PLLs located at each corner of the die. The Cyclone IV GX FPGA has I/O elements at the top, bottom, and right sides of the die, while the Cyclone IV E FPGA has I/Os on all four sides of the die. The left side of the Cyclone IV GX die has up to eight transceivers in two quads consisting of four transceivers per quad. The top and bottom of each transceiver quad features a multi-purpose PLL (MPLL) that can be used by the transceiver or, when available, by the FPGA fabric. Both architectures include highly efficient interconnect and low-skew clock networks, providing connectivity between logic structures for clock and data signals.

Key Features

Power
Embedded Multipliers
Memory Blocks
Clock Networks and PLLs
Configuration, Design Security, and Remote System Upgrades
SEU Mitigation

Connectivity

Transceivers
External Memory Interfaces
I/O Features
Signal Integrity

Tags: cyclone_iv, altera