Altera Cyclone FPGA Architecture Overview

atomar — Wed, 27 Jun 2012 00:25:58 GMT

Current Revision posted to Documents by atomar on 6/27/2012 12:25:58 AM

Cyclone FPGA Architecture

Abundant logic and memory resources, clock management circuitry, and advanced I/O capabilities are all available in Cyclone devices. The Cyclone architecture consists of vertically arranged logic elements (LEs), embedded memory blocks, and phase-locked loops (PLLs) that are surrounded by I/O elements (IOEs) (Figure 2). A highly efficient interconnect and low-skew clock network provide connectivity between each of these structures for clock and data signals.

EP1C20 Device Floorplan

Area-efficient IOEs are grouped into I/O banks around the device, offering significant capabilities while consuming minimal die area. They include support for a range of single-ended and differential I/O standards, such as SSTL-2, SSTL-3, and the LVDS I/O standard at up to 640 megabits per second (Mbps). Each IOE contains three registers for implementing double data rate (DDR) applications and associated circuitry for other I/O features like programmable drive strength, bus hold, and programmable slew rate.

The I/O banks are equipped with dedicated external memory interface circuitry. This circuitry simplifies data transfer with external memory devices, including DDR SDRAM and FCRAM devices. Maximum data transfer rates reach speeds of up to 266 Mbps (133-MHz clock). Cyclone devices are 32-bit/66-MHz PCI compliant. Each IOE provides multiple paths from the pin to the core, allowing the device to meet associated set-up and hold times.

Cyclone devices range in density from 2,910 LEs and 59,904 bits of RAM to 20,060 LEs and 294,912 bits of RAM.

Clock Distribution

Each Cyclone device is served by a global clock network composed of up to eight distinct clock lines. These clock lines are accessible from anywhere in the device and can be fed either by input pins, PLL outputs, DDR/PCI inputs, or internal logic.

Tags: fpga, altera