Freescale: DSP56800E Family Overview

atomar — Wed, 10 Jul 2013 07:48:51 GMT

Current Revision posted to Documents by atomar on 7/10/2013 7:48:51 AM

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Overview

The DSP56800E core architecture represents the next step in the evolution of Freescale’s 16-bit DSP56800 Family of digital signal controllers. It provides low-cost, low-power, mid-performance computing, combining DSC power and parallelism with MCU-like programming simplicity. The DSP56800E core is a general-purpose central processing unit, designed for both efficient digital signal processing and a variety of controller operations.

A powerful multiply-accumulate (MAC) unit, with optional rounding and negation, enables the efficient coding of DSC and digital filtering algorithms. The DSP56800E’s large register set, powerful addressing modes, and bit-manipulation unit allow traditional control tasks to be performed with ease, without the complexity and limitations normally associated with DSCs. Assisting in the coding of general-purpose programs is support for a software stack; flexible addressing modes; and byte, word, and long-word data types.

The DSP56800E Family is not a custom IC designed for a particular application; it is designed as a general-purpose DSC architecture to efficiently execute common DSC algorithms and controller code in minimal time.

The key attributes of a DSC are as follows:

Multiply-accumulate (MAC) operation
Fetching up to two operands per instruction cycle for the MAC
Flexibility in implementation through a powerful instruction set
Input/output capability to move data in and out of the DSC

The multiply-accumulate (MAC) operation is the fundamental operation used in DSC. The DSP56800E family of processors has a dual Harvard architecture that is optimized for MAC operations. Figure 1-5 shows how the DSP56800E architecture matches the shape of the MAC operation. The two operands, C() and X(), are directed to a multiply operation, and the result is summed. This process is built into the chip in that two separate data memory accesses are allowed to feed a single-cycle MAC. The entire process must occur under program control to direct the correct operands to the multiplier and to save the accumulated result, as needed. Since the memory and the MAC are independent, the DSC can perform two memory moves, a multiply and an accumulate, and two address updates in a single operation. As a result, many DSC benchmarks execute very efficiently for a single-multiplier architecture.

Ultra-Low Power

Kinetis MCUs feature the best in low power innovation, including ten flexible low-power operating modes for power profile optimization, power and clock gating, back-biasing, 4 μS wake up times, flash programming and analog peripheral operation down to 1.71V. The result is Stop and Run currents of <500 nA and <200μA/MHz respectively. A low-power RTC and low-leakage wake-up unit add further low power flexibility, while a low-power timer enables continual system operation in reduced power states.

Key Features

The DSP56800E core architecture extends Freescale’s DSP56800 Family architecture. It is source-code compatible with DSP56800 devices and adds the following new features:

Byte and long data types, supplementing the DSP56800’s word data type
24-bit data memory address space
21-bit program memory address space
Three additional 24-bit pointer registers (one of which can be used as an offset register)
A secondary 16-bit offset register to further enhance the dual parallel data ALU instructions
Two additional 36-bit accumulator registers
Full-precision integer multiplication
32-bit logical and shifting operations
Second read in dual read instruction can access off-chip memory
Loop count (LC) register extended to 16 bits
Full support for nested DO looping through additional loop address and count registers
Loop address and hardware stack extended to 24 bits
Three additional interrupt levels with a software interrupt for each level
Enhanced On-Chip Emulation (Enhanced OnCE) with three debugging modes:
- Non-intrusive real-time debugging
- Minimally intrusive real-time debugging
- Breakpoint and step mode (core is halted)

The advantages of using the DSC include the following:

Fewer components
Stable, deterministic performance
No filter adjustments
Wide range of applications
Filters with sharper filtering characteristics
High noise immunity
Adaptive filters are easily implemented
Self-test can be built in
Better power-supply rejection

Development Tools

Software Development Tools:

Tool Type	Supplier	MPN	Supported Family	Description
IDE	Freescale	CodeWarrior	All Freescale MCU's	Freescale's software and development solutions take you beyond the silicon, helping to bring your embedded applications to life. Learn More

Applications

Consumer
Industrial
Medical/Healthcare
Motor Control

Video

www.youtube.com/watch

Kits & Evaluation Modules

56800/E DSCs

Part Number	Core Architecture	Silicon Family	Description
MC56F8006DEMO-TMC56F8006DEMO-T	56800E	MC56F800x	MC56F8006DEMO-T Demonstration Board for MC56F8006 Digital Signal Controller
MC56F8037EVMMC56F8037EVM	56800E	MC56F803x	MC56F8037EVM DSC Evaluation Board
MC56F8323EVMEMC56F8323EVME	56800E	MC56F832x	MC56F8323EVME Evaluation Kit for MC56F832x and MC56F812x Digital Signal Controllers
TWR-56F8257TWR-56F8257	56800E	MC56F825x	TWR-56F8257 Motor Control MCU Module