<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/"><channel><title>Altera Overview</title><link>https://community.element14.com/products/devtools/technicallibrary/w/documents/9958/altera-overview</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>Altera Overview</title><link>https://community.element14.com/products/devtools/technicallibrary/w/documents/9958/altera-overview</link><pubDate>Mon, 15 Oct 2012 19:28:30 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:3aafe950-0de6-4b5b-b6f4-bb18cae6e10d</guid><dc:creator>atomar</dc:creator><comments>https://community.element14.com/products/devtools/technicallibrary/w/documents/9958/altera-overview#comments</comments><description>Current Revision posted to Documents by atomar on 10/15/2012 7:28:30 PM&lt;br /&gt;
&lt;div&gt; &lt;/div&gt;&lt;table border="0" cellpadding="3" cellspacing="0" class="jiveNoBorder" style="border:0px solid #000000;width:100%;"&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td style="border:0px solid black;border:0px solid #000000;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;text-align:left;color:#333333;"&gt;&lt;a href="/products/devtools/technicallibrary/w/documents/9456/development-kit-line-card---altera"&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/248x46/__key/communityserver-wikis-components-files/00-00-00-01-46/5344.contentimage_5F00_19942.png"&gt;&lt;img alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/5344.contentimage_19942.png-248x46.png?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=yjwOnFyPkVdsbfSFdKIxu6FzgCJTtVl7UtZIoGkCzcg%3D&amp;amp;se=2026-04-25T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=mZ2Xrr4/s2NzOnhYXCXV0w==" style="max-height: 46px;max-width: 248px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/a&gt;&lt;/td&gt;&lt;td style="border:0px solid black;border:0px solid #000000;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;text-align:left;color:#333333;"&gt;&lt;br /&gt;&lt;/td&gt;&lt;td style="border:0px solid black;border:0px solid #000000;text-align:right;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;color:#333333;"&gt;&lt;strike&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/300x300/__key/communityserver-wikis-components-files/00-00-00-01-46/6825.contentimage_5F00_19943.png"&gt;&lt;img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/6825.contentimage_19943.png-300x300.png?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=FEAv5DOa3ob4JSFHzSC76E6prwpEuxgZ9w0FZ49Cl6Q%3D&amp;amp;se=2026-04-25T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=WzhvIYclS0VAIw+sd/qu/g==" style="max-height: 300px;max-width: 300px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/strike&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;hr /&gt;&lt;p style="margin:0;"&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/264x62/__key/communityserver-wikis-components-files/00-00-00-01-46/1157.contentimage_5F00_19944.jpg"&gt;&lt;img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/1157.contentimage_19944.jpg-264x62.jpg?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=LerG%2BOA1aIcXIAMP5cz4qnnrjtOX1pePD6LK9C8d5%2F0%3D&amp;amp;se=2026-04-25T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=HaLjS5H2pilBX1UCa+7smg==" style="max-height: 62px;max-width: 264px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/p&gt;&lt;h2 style="font-size:1.7778em;font-family:&amp;#39;Lucida Grande&amp;#39;, Arial, Helvetica, sans-serif;"&gt;Overview&lt;/h2&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;&lt;strong&gt;Altera Corporation is the pioneer of programmable logic solutions, enabling system and semiconductor companies to rapidly and cost effectively innovate, differentiate, and win in their markets. Altera offers FPGAs, CPLDs, and ASICs in combination with software tools, intellectual property, and customer support to provide high-value programmable solutions to customers worldwide.&lt;/strong&gt;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;h3&gt;&lt;strong&gt;Altera FPGAs&lt;/strong&gt;&lt;/h3&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;The field-programmable gate array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows you to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field—hence the name &amp;quot;field-programmable&amp;quot;. You can use an FPGA to implement any logical function that an application-specific integrated circuit (ASIC) could perform, but the ability to update the functionality after shipping offers advantages for many applications.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;Unlike previous generation FPGAs using I/Os with programmable logic and interconnects, today&amp;#39;s FPGAs consist of various mixes of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and routing. Specifically, an FPGA contains programmable logic components called logic elements (LEs) and a hierarchy of reconfigurable interconnects that allow the LEs to be physically connected. You can configure LEs to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flipflops or more complete blocks of memory.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;As FPGAs continue to evolve, the devices have become more integrated. Hard intellectual property (IP) blocks built into the FPGA fabric provide rich functions while lowering power and cost and freeing up logic resources for product differentiation. Newer FPGA families are being developed with hard embedded processors, transforming the devices into systems on a chip (SoC).&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;Compared to ASICs or ASSPs, FPGAs offer many design advantages, including: &lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;ul&gt;&lt;li&gt;Rapid prototyping &lt;/li&gt;&lt;li&gt;Shorter time to market &lt;/li&gt;&lt;li&gt;The ability to re-program in the field for debugging &lt;/li&gt;&lt;li&gt;Lower NRE costs &lt;/li&gt;&lt;li&gt;Long product life cycle to mitigate obsolescence risk&lt;/li&gt;&lt;/ul&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;Altera offers customers a broad spectrum of FPGAs geared towards diverse markets and applications&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;table border="1" cellpadding="3" cellspacing="0" class="jiveBorder" style="border:1px solid #000000;width:100%;"&gt;&lt;thead&gt;&lt;tr class="tableizer-firstrow"&gt;&lt;th style="border:1px solid black;border:1px solid #000000;text-align:center;font-family:arial, helvetica, sans-serif;padding:3px;background-color:transparent;color:#333333;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10126/altera-cyclone-fpga-series-overview"&gt;Cyclone FPGAs&lt;/a&gt;&lt;/strong&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;text-align:center;font-family:arial, helvetica, sans-serif;padding:3px;background-color:transparent;color:#333333;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10096/altera-arria-fpga-series-overview"&gt;Arria FPGAs&lt;/a&gt;&lt;/strong&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;text-align:center;font-family:arial, helvetica, sans-serif;padding:3px;background-color:transparent;color:#333333;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10124/altera-stratix-fpga-series-overview"&gt;Stratix FPGAs&lt;/a&gt;&lt;/strong&gt;&lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:justify;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;p style="margin:0;"&gt;Cyclone&lt;span class="emoticon" data-url="https://community.element14.com/cfs-file/__key/system/emoji/00ae.svg" title="Registered"&gt;&amp;#x00ae;&lt;/span&gt; series FPGAs are the industry&amp;#39;s lowest cost, lowest power FPGAs, ideal for high-volume, cost-sensitive applications.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;Use a Cyclone series FPGA alone, as a digital signal processor, or as a cost-effective embedded processing solution. Cyclone series FPGAs offer a wide range of density, memory, embedded multiplier, and packaging options. Newer families include integrated transceiver options (at data rates up to 5G).&lt;/p&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:justify;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;p style="margin:0;"&gt;Arria&lt;span class="emoticon" data-url="https://community.element14.com/cfs-file/__key/system/emoji/00ae.svg" title="Registered"&gt;&amp;#x00ae;&lt;/span&gt; series FPGA provide an optimal balance of performance, power, and price for mid-range transceiver-based applications. You&amp;#39;ll find a rich feature set of functions (memory, logic, and DSP) combined with superior signal integrity in the devices.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;Arria series FPGAs feature on-chip transceivers that allow you to integrate more functions and maximize system bandwidth (at data rates up to 10G).&lt;/p&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:justify;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;p style="margin:0;"&gt;Stratix&lt;span class="emoticon" data-url="https://community.element14.com/cfs-file/__key/system/emoji/00ae.svg" title="Registered"&gt;&amp;#x00ae;&lt;/span&gt; series FPGAs are the industry&amp;#39;s highest bandwidth, highest density FPGAs, ideal for high-end applications. Newer families come with integrated transceiver options (at data rates up to 28G).&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;Stratix series FPGAs simplify the challenges of signal integrity by providing transceivers with best-in-class jitter characteristics. Features such as Programmable Power Technology keep total power in check.&lt;/p&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;&lt;strong&gt;&lt;br /&gt;&lt;/strong&gt;&lt;/p&gt;&lt;h3 style="text-align:justify;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10084/altera-max-cpld-series-overview"&gt;Altera Low-Cost MAX CPLD&lt;/a&gt;&lt;/strong&gt;&lt;/h3&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;Building on a reputation earned since their introduction in 1993, Altera&amp;#39;s MAX&lt;span class="emoticon" data-url="https://community.element14.com/cfs-file/__key/system/emoji/00ae.svg" title="Registered"&gt;&amp;#x00ae;&lt;/span&gt; CPLD series provides you with the lowest power, lowest cost CPLDs.&lt;strong&gt;&lt;br /&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;table border="1" cellpadding="3" cellspacing="0" class="jiveBorder" style="border:1px solid #000000;width:80%;"&gt;&lt;thead&gt;&lt;tr&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;&lt;br /&gt;&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;MAX 7000S&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;MAX 3000A&lt;br /&gt;&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10097/altera-max-ii-cpld-architecture-overview"&gt;&lt;span style="color:#ffffff;"&gt;MAX II&lt;/span&gt;&lt;/a&gt;&lt;br /&gt;&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;MAX IIZ&lt;br /&gt;&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;th style="border:1px solid black;border:1px solid #000000;font-family:arial, helvetica, sans-serif;padding:3px;text-align:-webkit-center;background-color:#6690bc;color:#333333;"&gt;&lt;span style="color:#ffffff;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="https://www.element14.com/community/docs/DOC-46662/l/altera-max-v-cpld-architecture-overview"&gt;&lt;span style="color:#ffffff;"&gt;MAX V&lt;/span&gt;&lt;/a&gt;&lt;br /&gt;&lt;/strong&gt;&lt;/span&gt;&lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td style="border:1px solid black;border:1px solid #000000;background-color:transparent;padding:3px;text-align:left;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;&lt;strong&gt;Year of Introduction&lt;/strong&gt;&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;1995&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;2002&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;2004&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;2007&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;2010&lt;/td&gt;&lt;/tr&gt;&lt;tr&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:left;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;&lt;strong&gt;Process Technology&lt;/strong&gt;&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;0.5 µm&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;&lt;span style="color:#000000;"&gt;0.30 µm&lt;/span&gt;&lt;br /&gt;&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;0.18 µm&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;0.18 µm&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;0.18 µm&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;&lt;tr&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:left;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;&lt;strong&gt;Key Features&lt;/strong&gt;&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;5.0-V I/Os&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;Low cost&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;I/O count&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;Zero power&lt;/span&gt;&lt;/td&gt;&lt;td style="border:1px solid black;border:1px solid #000000;text-align:center;background-color:transparent;padding:3px;color:#000000;"&gt;&lt;span style="color:#000000;"&gt;Low cost and power&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="https://www.element14.com/community/docs/DOC-46662/l/altera-max-v-cpld-architecture-overview"&gt;MAX V CPLD&lt;/a&gt;&lt;/strong&gt; - The newest in our CPLD series, delivers the market&amp;#39;s best value. Featuring a unique, non-volatile architecture and one of the industry&amp;#39;s largest density CPLDs, MAX V devices provide robust new features at lower total power compared to competitive CPLDs. They&amp;#39;re ideal for general purpose and portable designs in a wide variety of market segments, including wireline, wireless, industrial, consumer, computer/storage, automotive, broadcast, and military.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;&lt;strong&gt;&lt;a class="jive-link-wiki-small" href="/products/devtools/technicallibrary/w/documents/10097/altera-max-ii-cpld-architecture-overview"&gt;MAX II CPLD&lt;/a&gt;&lt;/strong&gt; - Bbased on the same groundbreaking architecture, delivers low power and low cost per I/O pin. MAX II CPLDs are instant-on, non-volatile devices that target general-purpose, low-density logic and portable applications, such as cellular handset design. The MAX II CPLD also drives power and cost improvements to higher densities, enabling you to use a MAX II CPLD in place of a higher power or higher cost ASSP or standard-logic CPLD.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;&lt;strong&gt;Zero power MAX IIZ CPLDs - &lt;/strong&gt;offer the same non-volatile, instant-on advantages found in the MAX II CPLD family and are applicable to a wide range of functions.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;&lt;strong&gt;MAX 3000A CPLD - &lt;/strong&gt;Is cost-optimized for high-volume applications. Manufactured on an advanced 0.30-µm CMOS process, the EEPROM-based MAX 3000A CPLD family provides instant-on capability and offers densities from 32 to 512 macrocells. MAX 3000A CPLDs support in-system programmability (ISP) and can be easily reconfigured in the field. Each MAX 3000A macrocell is individually configurable for either sequential or combinatorial logic operation.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;&lt;strong&gt;The 5.0-V I/O MAX 7000S CPLD family&lt;/strong&gt; is critical for industrial, military, and communication systems that require 5.0-V I/Os.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;text-align:justify;"&gt;&lt;strong&gt;&lt;br /&gt;&lt;/strong&gt;&lt;/p&gt;&lt;p style="margin:0;text-align:right;"&gt;&lt;a class="jive-link-anchor-small" href="#top"&gt;Back to top&lt;/a&gt;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;hr /&gt;&lt;table border="0" cellpadding="3" cellspacing="0" class="jiveNoBorder" style="border:0px solid #000000;width:100%;"&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td style="border:0px solid black;border:0px solid #000000;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;text-align:left;color:#333333;"&gt;&lt;a href="/products/devtools/technicallibrary/w/documents/9456/development-kit-line-card---altera"&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/248x46/__key/communityserver-wikis-components-files/00-00-00-01-46/5344.contentimage_5F00_19942.png"&gt;&lt;img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/5344.contentimage_19942.png-248x46.png?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=yjwOnFyPkVdsbfSFdKIxu6FzgCJTtVl7UtZIoGkCzcg%3D&amp;amp;se=2026-04-25T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=mZ2Xrr4/s2NzOnhYXCXV0w==" style="max-height: 46px;max-width: 248px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/a&gt;&lt;/td&gt;&lt;td style="border:0px solid black;border:0px solid #000000;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;text-align:left;color:#333333;"&gt;&lt;br /&gt;&lt;/td&gt;&lt;td style="border:0px solid black;border:0px solid #000000;text-align:right;font-family:arial, helvetica, sans-serif;background-color:transparent;padding:3px;color:#333333;"&gt;&lt;strike&gt;&lt;span&gt;&lt;a href="https://community.element14.com/resized-image/__size/300x300/__key/communityserver-wikis-components-files/00-00-00-01-46/3276.contentimage_5F00_19945.png"&gt;&lt;img loading="lazy" alt="image" src="https://community-storage.element14.com/communityserver-components-secureimagefileviewer/communityserver/wikis/components/files/00/00/00/01/46/3276.contentimage_19945.png-300x300.png?sv=2016-05-31&amp;amp;sr=b&amp;amp;sig=qj9U%2B2gLlM5hRoClmBYIMykTnsFQ8QWjJjXHmsR%2BeH0%3D&amp;amp;se=2026-04-25T23%3A59%3A59Z&amp;amp;sp=r&amp;amp;_=WzhvIYclS0VAIw+sd/qu/g==" style="max-height: 300px;max-width: 300px;" /&gt;&lt;/a&gt;&lt;/span&gt;&lt;/strike&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;hr /&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;
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