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Circuit studio v1.4 not generating correct Netlists

cpallan

I am using Circuit Studio v.1.4 and am having problems generating a correct netlist from a hierarchical design. The netlist is generated, but the parent sheet nets are not connected to the child sheet nets.

 

I have compiled the design, and then <ctrl> double-click on the sheet entry, and it takes me to that highlighted net in the child sheet. So it appears that the nets are connected. But when I create a netlist, the nets of the top level sheet and the nets in the child sheets are not connected. Why is this? I have checked the names / types of sheet entries and they are the same (no mis-spellings), and as I said, the child sheet net appears when I <crtl> double click.

 

Thanks for any help on this issue.

Regards,

Charlie Allan

  • 0 in reply to e14softwareteam

    From the developers:

     

    Just confirming you have done this:

    To check your connections, use Home > Project > Compile and then hold the Ctrl key while double clicking the Sheet Entry. This will take you to the sub sheet and will temporarily mask out other nets, effectively highlighting the net you are interested in. Then if you go back to the top sheet you should see that Sheet Entry and the wire connected to it highlighted, to indicate the wire is connected to the Sheet Entry.

     

    If your design is updated to a new blank PCB, do the nets appear to be connected? Is that why you're generating a netlist, to check for a problem?

     

    How are you generating the netlist?

     

    If using EDIF, rather than using the button on the Outputs tab, use the following method:

    Open any schematic in the project and click in the search bar at the top right of the screen and type netlist

    click:

    Netlist for Project >EDIF for PCB and this will create an EDF file with the same name as the schematic but it will actually be for the whole project.

  • 0 in reply to e14softwareteam

    I'm generating a netlist for two reasons: 1) to check for any connection problems, and 2) to send out for board design / layout (I'm not doing this myself).

     

    Your method of creating a netlist (enter netlist into help and select "Netlist for Projecct >EDIF for PCB") works to generate a netlist for the complete design. Thank you.

     

    Questions:

    1) Why does the button on the Outputs tab generate a netlist for only the top level sheet in the design

    2) When I select the "report single pin nets" from the outputs tab, it shows all of the nets that go only to the child sheets as single pin nets, when in fact they are not; they are connected in the child sheets. Why is this? How do I get a single pin net report for the whole project?