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<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/"><channel><title>Getting Started with CircuitStudio: (#10) Running Design Rule Checks</title><link>https://community.element14.com/products/manufacturers/altium/w/documents/2957/getting-started-with-circuitstudio-10-running-design-rule-checks</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>Getting Started with CircuitStudio: (#10) Running Design Rule Checks</title><link>https://community.element14.com/products/manufacturers/altium/w/documents/2957/getting-started-with-circuitstudio-10-running-design-rule-checks</link><pubDate>Thu, 08 Jun 2017 11:36:40 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:e3d60660-3724-4cb2-83f0-99796f14d7eb</guid><dc:creator>e14softwareuk</dc:creator><comments>https://community.element14.com/products/manufacturers/altium/w/documents/2957/getting-started-with-circuitstudio-10-running-design-rule-checks#comments</comments><description>Current Revision posted to Documents by e14softwareuk on 6/8/2017 11:36:40 AM&lt;br /&gt;
&lt;p style="margin:0;"&gt;When new to the software, a long list of DRC violations can initially seem overwhelming. A good approach to managing this is to disable and enable rules in the Design Rule Check dialog at different stages of the design process. It is not advisable to disable the design rules themselves, just the checking of them. For example, you would always disable the Un-Routed Net check until the board is fully routed.&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;&lt;/p&gt;&lt;span&gt;&lt;a href="https://www.youtube.com/watch?v=Rt__uqDO6SE"&gt;www.youtube.com/watch&lt;/a&gt;&lt;/span&gt;&lt;p style="margin:0;"&gt;&lt;/p&gt;&lt;p style="margin:0;padding:0px;"&gt;&amp;nbsp;&lt;/p&gt;&lt;p style="margin:0;"&gt;&lt;span style="font-family:Verdana, &amp;#39;Verdana Ref&amp;#39;, Geneva, Tahoma, sans-serif;color:#333333;"&gt;&lt;a class="jive-link-wiki-small" href="/products/manufacturers/altium/w/documents/2958/getting-started-with-circuitstudio-11-generating-manufacturing-data"&gt;Next Video&lt;/a&gt; • &lt;/span&gt;&lt;a class="jive-link-wiki-small" href="/products/manufacturers/altium/w/documents/2947/getting-started-with-circuitstudio-video-tutorial-series" style="font-family:Verdana, &amp;#39;Verdana Ref&amp;#39;, Geneva, Tahoma, sans-serif;color:#007fac;"&gt;Table of Contents&lt;/a&gt;&lt;/p&gt;
&lt;div class="migration-injected-attachments"&gt;&lt;div style="font-weight:bold;margin:15px 0 5px 0;"&gt;Attachments:&lt;/div&gt;&lt;div&gt;&lt;/div&gt;&lt;table style="border:0;"&gt;&lt;tbody&gt;&lt;tr&gt;&lt;td width="160"&gt;&lt;span class="_se_attachment" id="attid_https://www.element14.com/community/api/core/v3/attachments/239502"&gt;&lt;a href="https://community.element14.com/cfs-file/__key/communityserver-wikis-components-files/00-00-00-01-30/10_2D00_DisplayingandResolvingDesignRuleViolations.pdf"&gt;community.element14.com/.../10_2D00_DisplayingandResolvingDesignRuleViolations.pdf&lt;/a&gt;&lt;/span&gt;&lt;/td&gt;&lt;td&gt;&lt;span style="font-size:80%;"&gt;10-DisplayingandResolvingDesignRuleViolations.pdf&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;&lt;/tbody&gt;&lt;/table&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;
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