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RE: Introducing the AMD Spartan™︎ UltraScale+™︎ FPGAs for Secure, Low-power, High I/O Count Applications

bhfletcher — Thu, 10 Jul 2025 00:02:46 GMT

The first three devices in the Spartan UltraScale+ family are in volume production! This includes the SU10P, SU25P, and SU35P. These smaller devices do not have transceivers or the hardened memory controller, but they do have the new security and configuration features, as well as 200-300 I/Os!

www.amd.com/.../spartan-ultrascale-plus-fpgas-in-production.html

RE: Introducing the AMD Spartan™︎ UltraScale+™︎ FPGAs for Secure, Low-power, High I/O Count Applications

embeddedguy — Sun, 06 Jul 2025 06:38:16 GMT

Nice Article.

RE: Introducing the AMD Spartan™︎ UltraScale+™︎ FPGAs for Secure, Low-power, High I/O Count Applications

venkat01 — Wed, 02 Jul 2025 18:07:24 GMT

There are some interesting changes with the configuration and boot architecture for the Spartan Ultrascale+ FPGAs with the Platform Management Controller and using the Programmable Device Image ( .pdi) file instead of the .bit file, making the boot process more robust and secure.

RE: Reserve Time to Attend the Xilinx Adapt Virtual Event on Learning the Vivado Design Suite (Feb 10 & 11th, 2021)

14rhb — Wed, 10 Feb 2021 19:09:31 GMT

Day 1 had some great presentations - there were snippets of information on using Vivado that I wasn't aware of such as joining IP into a higher level block design that simplified the overall design.

RE: Reserve Time to Attend the Xilinx Adapt Virtual Event on Learning the Vivado Design Suite (Feb 10 & 11th, 2021)

14rhb — Tue, 09 Feb 2021 19:09:04 GMT

Thank you, the course looks very interesting and the timings work for me also. Registration was very easy....I now just need to remember to log on and take part !

RE: Highlights of the Xilinx Developer Forum, San Jose, CA

14rhb — Tue, 08 Oct 2019 20:37:24 GMT

Caffe and TensorFlow have cropped up in my BB-AI learning so its great to get onboard with this new technology, even just a basic understanding. On a separate and light-hearted note, we are moving into configurable logic with AI and ML elements....what's the phrase they used? "Self-awareness" I think they called it [View:/resized-image/__size/16x16/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-9a335b0e-8ed5-459b-a37f-8f199c9d6a66/5672.contentimage_5F00_403.png:16:16]

RE: Highlights of the Xilinx Developer Forum, San Jose, CA

14rhb — Tue, 08 Oct 2019 20:30:33 GMT

A great summary, thank you. Did the Xilinx experts have any view on the future of PYNQ project support with the advent of Vitis?

RE: Highlights of the Xilinx Developer Forum, San Jose, CA

dubbie — Mon, 07 Oct 2019 10:24:00 GMT

An informative summary of the conference. The TurtleBot3 Burger seems like my dream mobile robot.

Dubbie

RE: Highlights of the Xilinx Developer Forum, San Jose, CA

neuromodulator — Mon, 07 Oct 2019 06:30:26 GMT

Very interesting! I hope Digilent has plans to release and roadtest new FPGA products.

RE: Highlights of the Xilinx Developer Forum, San Jose, CA

mudz — Mon, 07 Oct 2019 05:28:14 GMT

FPGA next Gen Horse Powers!! Nice event..

p.s - Pics taken from - [View:/resized-image/__size/16x16/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-9a335b0e-8ed5-459b-a37f-8f199c9d6a66/contentimage_5F00_403.png:16:16]

[View:/resized-image/__size/624x351/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-9a335b0e-8ed5-459b-a37f-8f199c9d6a66/contentimage_5F00_204800.jpg:624:351]

RE: Highlights of the Xilinx Developer Forum, San Jose, CA

ralphjy — Mon, 07 Oct 2019 00:15:20 GMT

Sounds like it was a great event! Would love to get one of those Turtlebot3 Burgers [View:/resized-image/__size/16x16/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-9a335b0e-8ed5-459b-a37f-8f199c9d6a66/contentimage_5F00_1.png:16:16]. Looking forward to starting the Path II Programmable training. Vitis sounds like it will be very helpful when it becomes available.

RE: A first taste of Zynq UltraScale+ MPSoC #overview of the family

genebren — Sat, 29 Dec 2018 20:35:12 GMT

This was a nice overview of the Zynq UltraScale+ product. I too would question the conclusion of the future being AI driven. Engineers and/or designers have (or should have) a full tool box of approaches and techniques available when designing. There is now, and most likely in the future will be, a need for everything from bare-metal to full blown AI and everything in between.

Gene

RE: A first taste of Zynq UltraScale+ MPSoC #overview of the family

DAB — Sat, 29 Dec 2018 20:02:05 GMT

Nice overview, but I dispute your conclusion that the future is AI driven.

AI is a part of the solution, but there are many applications for which it is unsuited.

DAB

RE: A Taste of the Xilinx Developer Forum (XDF) 2018 in San Jose

dougw — Mon, 08 Oct 2018 16:25:44 GMT

I have an interest in augmented reality, mixed reality and virtual reality. There are significant issues with latency, depth alignment and parallax that will require serious horsepower to tackle. Maybe ACAP will be a step in the right direction for these applications.