Forum - Recent Threads

Learn about the new AMD Kintex UltraScale+ Gen 2 FPGA Family!

bhfletcher — Thu, 19 Feb 2026 16:11:06 GMT

Hello E14 community!

AMD recently announced Kintex UltraScale+ Gen 2 FPGAs, a new mid-range FPGA family. You can read about it in this Blog.

Next week on Feb 25, I will present an overview of the family architecture and answer questions. Please register and join me!

https://webinar.amd.com/Outscale-Your-Competition-with-the-New-AMD-Kintex-tm-UltraScale-tm-Gen-2-FPGA-Family/en/registration

Thanks,

Bryan

TAA Compliance for parts

colsa — Wed, 05 Apr 2023 12:30:42 GMT

Is EK-VCK190-G and EK-VMK180-G TAA COMPLIANT?

Importing Arduino library files into PYNQ?

kevin_v — Fri, 22 May 2020 00:55:54 GMT

Hello,

Does anyone here have experience with taking Arduino .h file type and was able to modify it to be used with pynq and juptyer? If so, could you include a modified file and the original file it was based off of, so i can take a look at both to understand what changes are needed to be made.

I know there is a document on the pynq website that explains how to make a header files but at least for me its not easy to follow. Here is the link to the document i am referring to:

https://pynq.readthedocs.io/en/latest/overlay_design_methodology/pynq_microblaze_subsystem.html?_ga=2.228378772.86472398…

Thanks

Problem with PYNZ-Z2 and HDMI output from camera

Fred27 — Fri, 10 Apr 2020 09:15:02 GMT

I'm currently making sure I'm in a good position to hit the ground running with the upcoming PYNQ-Z2 workshops. I bought the recommended kit including an Apeman A77 camera and thought I'd just have a quick poke around in advance. I ran through the "getting started" and the Pynq 2.5 image includes some simple HDMI examples. (I hope I'm not jumping too far ahead, but like to be prepared.)

Anyway, as I start to run the HDMI example I get a kernel died error (as shown). You can see on screen what's been run. This is just wiring HDMI out to show what's on HDMI in. The error is completely repeatable. Nothing noteworthy in /var/log/jupyter.log to give any clue.

As quick Google suggested that maybe the image is too high resolution, and when I checked the camera on my TV it outputs 1080p at 60fps regardless of the resolution of video being captured. Could 1080p be too much? Time to switch to a Raspberry Pi 4 where I can change resolution properly. The above example ran quite happily with the Pi at a lower resolution, but surprised me when it also ran using the Pi at 1920x1080 at 60fps too.

Is this camera (Apeman A77) compatible with the HDMI on the PYNQ-Z2? I'd have expected it to be as it was the recommended kit and the Crosstour one listed now is essentially the same model.

I'll try to do more digging into any subtle differences between the HDMI output of the Pi and the camera, but all I have is a TV that shows some info on the input. Anyone else have any ideas?

SQRL Acorn as Artix-7 dev board?

Fred27 — Thu, 09 Apr 2020 13:14:39 GMT

I keep seeing SQRL Acorn CLE-215 boards appearing on eBay. From what I can tell they were intended for crypto mining, but didn't go down well due to the necessary software not appearing. Cue a lot of angry people and boards being sold on eBay.

Considering it's an Artix-7 and it has a M.2 interface plus a JTAG header, I was wondering if this would make an interesting board to play around with. My gut feel is that any PCIe work is probably advanced stuff and that it would end up gathering dust. Just thought I'd ask and maybe put others onto a good deal - at eBay prices that is, not the original selling price.

Link to manufacturer: Acorn CLE-215 | SQRL

Anyone have an opinion?

Ideas: Capturing Data into RAM/BRAM/DDR3?

14rhb — Wed, 25 Sep 2019 16:41:50 GMT

I would be really grateful for some initial ideas from the FPGA/E14 experts as to how I can do the following: I'm happy to struggle on learning and writing the scripts needed but I really haven't got an idea which method should be used. This learning is for my Z7k Logic Analyser: concepts where I eventually want to be able to capture the voltage changes on some input pins at a very high clock rate (say 100MHz) directly into RAM and in slower time to be able to sift through them using the PS to do analysis - for example to display the hexadecimal equivalent or if it were UART data to give the user the values in that.

I've explored the idea of BRAM and being able to read/write to it from the PS: Z7k Logic Analyser: progress update and I've also just managed to follow an online tutorial where the author implements a FIFO to pass DMA data to and read it back from: Z7k Logic Analyser: Progress Update #2

My current thinking is that I need to make my own AXI-4 IP block, as previously, that fills up with the serial data. I'm also thinking that will be limited somewhat due to limitations in BRAM sizes whereas the DDR3 on the ZC702 is massive and could store so much more of the signal.

Does anyone please have any suggestions on what could be the better approach? Thank you.

Using multiple Xilinx Series-7 transceivers from the same quad separately.

rachaelp — Thu, 11 Jul 2019 14:09:40 GMT

Hi All,

I've got a design using a Kintex-7 FPGA. I have a single channel transceiver up and running and I have tested that all the transceiver channels work in the board individually but now I am trying to get all four transceivers up and running at once and am having issues.

So I created the original transceiver with the 7-Series FPGAs transceiver wizard from the IP catalog, chose the protocol I need, clock rates, line rate, etc, included the shared logic in the core. I then wrote some initialization and monitoring state machines to control the transceiver and make sure it all comes up correctly and it works. So, when I wanted to scale this up to 4 identical but independent channels, I took a copy of the IP and changed it so it didn't include the shared logic in the core and instantiated 3 copies of this. I then hooked up all the out's from the original transceiver to the corresponding ins of the new transceivers to get all the shared clocking buried in the first instance connected up to the new instances. I then replicated all the state machines and slaved the ones for the new transceivers to the first so they don't start their initialization until all the clocking and everything is good on the first and that's up and running. It all builds and the first transceiver still works fine, but unfortunately none of the newly added transceivers do anything at all and their outputs are stuck at 0. Has anybody else here got experience with these transceivers and managed to get a similar setup working? Any pointers would be much appreciated!

Many thanks,

Rachael

FMC Connectors

14rhb — Wed, 08 May 2019 09:21:54 GMT

I was trying to make a breakout board for the Xilinx ZC702 and specifically to be able to utilise the FMC pinouts. I believe the board uses the Samtec ASP-134603-01ASP-134603-01 Low Pin Count (LPC) connector but looking at their website I am uncertain what the mating part is. I've narrowed it down to ASP-134604-04 or ASP-134606-04 (the leaded option rather than lead-free) - the difference is described as:

VITA Standards specify configurations for the SEARAY™ High-Speed Array VITA 57.1 FPGA Mezzanine Card (FMC) connector in 8.5 mm and 10 mm stack heights.

But I cannot work out what that actually means and which I should buy. Any advice would be appreciated.

Rod

Recommended: Digital System Design With FPGA: Implementation Using Verilog And VHDL

rscasny — Sun, 04 Feb 2018 21:21:23 GMT

If you are interested in learning more about designing with FPGAs, I'd recommend getting the book, Digital System Design With FPGA: Implementation Using Verilog And VHDL.

It discusses the development and deployment of FPGA-based digital systems using Verilog and VHDL. The book offers a solid foundation in FPGA principles, practices, and applications and more. It has real-world examples (some will be featured in our FPGA Essentials), ready-to-run code, and inexpensive start-to-finish projects for both the Basys and Arty boards.

If you would like to purchase the book, click here.

When Should You Use an FPGA in an Embedded Design?

rscasny — Wed, 24 Jan 2018 21:54:18 GMT

The simple answer is if you need some glue logic around (IOs), or you require multiple processors/GPUs due to the required performance. The more involved answer involves a combination of security, ease-of-use, analog, power, and/or the use of FPGAs vs. SoCs. Read more about this topic by clicking here.