https://community.element14.com/products/manufacturers/cypress/w/documents/6353/cypress---an57821---circuit-board-layout-considerations-for-psoc-3-and-psoc-5en-USTelligent Community 12https://community.element14.com/products/manufacturers/cypress/w/documents/6353/cypress---an57821---circuit-board-layout-considerations-for-psoc-3-and-psoc-5Thu, 07 Oct 2021 01:59:20 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:1811dfdd-22f5-431c-9944-02f25fc9c793tech6https://community.element14.com/products/manufacturers/cypress/w/documents/6353/cypress---an57821---circuit-board-layout-considerations-for-psoc-3-and-psoc-5#commentsCurrent Revision posted to Documents by tech6 on 10/7/2021 1:59:20 AM<br /> <p style="margin:0;"><strong>Introduction</strong></p><p style="margin:0;padding:0px;">&nbsp;</p><p style="margin:0;">Until recently, most ADCs available in microcontrollers were restricted to 8 to 12 bits. Product families such as the PSoC<img alt="image" class="migration-embeded-object" src="#https://www.element14.com/community//files1.element14.com/community/9.0.5.998b920/images/emojis/00ae.png" /> 3 and 5 have made available ADCs with resolutions up to 20 bits. The simple rules of adding bypass capacitors and wide power supply traces are not sufficient when designing circuit boards with these higher performance ADCs. This application note helps to sensitize the designer when a PCB layout causes offsets and noise in the system.</p><p style="margin:0;padding:0px;">&nbsp;</p><p style="margin:0;"><strong><em>Last Updated:</em></strong> 12/10/2009</p><p style="margin:0;"><strong>Author:</strong> Mark Hastings</p><p style="margin:0;padding:0px;">&nbsp;</p><ul><li><a class="jive-link-external-small" href="http://www.cypress.com/?docID=19797" rel="nofollow ugc noopener" target="_blank"><span class="jive-icon-sml jive-icon-doctype-acrobat"></span>AN57821.pdf</a> (360.4 K)</li></ul><div style="clear:both;"></div> <div style="font-size: 90%;">Tags: psoc3, at:applicationnote, psoc5, sp:cypress</div>