Scrutinize my FPGA PCB Layout

RE: Scrutinize my FPGA PCB Layout

jc2048 — Thu, 14 Jul 2022 22:04:40 GMT

Just remembered that my Lattice Brevia-2 dev board has an asynchronous SRAM on it. This is how they've done it, in case you're interested ('they' being a 3rd-party design company - it wasn't done by Lattice themselves).

No termination resistors. They've placed the SRAM close to the side of the FPGA, so that the traces are short. As you can see, though, they have length-matched the traces. It's an IDT device with a min cycle time of 15ns (read or write), but I've got no idea what the cycle time actually being used is. I could put the demo back on it and scope some of the signals if you wanted.

RE: Scrutinize my FPGA PCB Layout

michaelkellett — Thu, 14 Jul 2022 10:04:58 GMT

Hello Shabaz,

I've had good results using TQFP FPGAs (Lattice XP2) with both static ram and SDRAM. In neither case have I used length equalised tracks or terminating resistors.

The SDRAM clock was 100MHz.

In both cases I chose general purpose IO pins based exclusively on pcb routing convnenience.

The pic is an example (from 2010) of a prototype pcb with a 208 pin TQFP connected to to asynchronous static ram chips.

Design rules were 0.15mm track and gap, 0.55mm vias with 0.2mm holes.

The two inner power plane layers are not shown.

The Spartan 7 has more routing resource than the Lattice XP2 (which is a very old design)

Of course you would absolutely not get away with this with modern DDRAM with its fast clocks and the need to use specific pins on the chip to work with Xilinx's hard interface and IP.

RE: Scrutinize my FPGA PCB Layout

rachaelp — Wed, 13 Jul 2022 20:15:04 GMT

Hi Shabaz!

At first glance it looks good so far! Your approach to breaking out the BGA and connecting up power/ground are good. How much of the IO do you think you'll use when you've added everything you want? If it's going to be a large portion of them you might need to be careful how you route out to make sure you retain enough routing channels and don't end up blocking yourself, but judging by how you've started it looks like you have the logical/methodical approach in hand anyway so I expect you'll be fine :)

RE: Scrutinize my FPGA PCB Layout

wolfgangfriedrich — Wed, 13 Jul 2022 12:18:58 GMT

Some comments and questions:

- A good rule of thumb is that traces into BGA pads can use up to 25% of the circumference of the pad. With a 0.4mm pad you can use 0.3mm (12mil) width for the power and gnd traces. And 0.127mm (5mil) signal traces might help with pricing at the budget board houses as well.
- Pad layout looks good in general, vias under the BGA shall be tented with soldermask to avoid shorting to neighboring balls. What are the 7 pads of the FPGA with white circles around them and the 4 horizontal lines? If they are silkscreen, they should be removed.
- Any BGA IO pin that is not used should not have a fan-out trace and via. Un-needed holes in the planes on layout 2 and 3 can be avoided that way.
- I did not check the Xilinx part for a dedicated SRAM interface, but assuming you are just using GPIOs of the FPGA for the SRAM interface you could align them much better to the SRAM pins. Having trace from the top row of the SRAM going to the bottom half of the BGA are more difficult to route, than having as many traces as possible running horizontally and then to a close IO pin. Cross-talk is not a major concern with a reference plane underneath.
- For power supply integrity it is better to have one ground plane and one power plane going all the way between the IO banks of the FPGA and the memory chip. Every time signals cross from top to bottom, as decoupling cap should stitch power and GND together, so it is useful to group signals that cross sides together. Is the SRAM 3.3V or 1.8V?
- At least the clock signal to the SRAM should have a series termination resistor. Ideally all signals should be terminated if EMC is a requirement. There are 4-packs of resistors in small packages. Moving the SRAM further away and lengthen the traces is a trade-off well worth for this. The resistor packs are ugly to hand-solder though.
- Soldering the board by hand seems doable with either a reflow oven or hot plate and a decent temp profile. If you decide to have the board assembled by a company, add two local fiducials at 2 opposite sides of the FPGA, the pick&place with thank you :).
- Shall we start a flame-war about odd angle traces ;)

- Review of the schematic in context to the layout might add some more insights, if you are willing to share it.

- Moving the 1.0V regulator to the 10 o'clock position around the FPGA seems to lead to a more efficient power flow.

RE: Scrutinize my FPGA PCB Layout

neuromodulator — Wed, 13 Jul 2022 06:43:48 GMT

I haven't tried a design around of ICs of the complexity of the ones that you want to use, but I found 2 sources that give some pretty good advice on how to design these kind of PCBs. One is a video of Rick Hartley about grounding (www.youtube.com/watch, were he discusses all about different stackups. One thing he shows in that video is that referencing signals to a power plane is not that good (i.e referencing to ground is much better). Of course in the end it all depends on each case, and there are going to be always tradeoffs, or time where you will have to break the best practices. One nice blog where the author explores designs that are less than ideal is a blog by Jay Carlson (https://jaycarlson.net/embedded-linux/). There he shows a couple of interesting things:
- It is possible to solder 0.65 pitch at home with a hot-plate.
- 4 layers is enough to get relatively complex BGAs to work (although they may not be EMC ideal)
- Memory track-length matching is much more forgiving than what manufacturers recommend.

RE: Scrutinize my FPGA PCB Layout

Jan Cumps — Tue, 12 Jul 2022 23:46:09 GMT

the FPGA is connected to a RAM chip (SRAM) on the right side. This is easier than DRAM. It’s messily routed currently.

You may have to length-match the RAM data lines (it may limit the achievable data rate if you don't), and the sets of balanced analogue inputs.

RE: Scrutinize my FPGA PCB Layout

Jan Cumps — Tue, 12 Jul 2022 23:32:12 GMT

Checking if [mention:7d5ee4caf55f4ccaa8b711eb508ecedd:e9ed411860ed4f2ba0265705b8793d05] can chime in. She's been doing FPGA design and BGA fanout as a job.

RE: Scrutinize my FPGA PCB Layout

dougw — Tue, 12 Jul 2022 23:11:14 GMT

SparkFun wrote an interesting article on how they laid out an 81 ball BGA (Artemis) in 4 layers, including all the "rules" they followed:

https://www.sparkfun.com/news/3122?_ga=2.220878495.625515125.1657666606-595437000.1657666606

RE: Scrutinize my FPGA PCB Layout

Andrew J — Tue, 12 Jul 2022 22:04:55 GMT

Can I assume the FPGA / SRAM signals are going to be high frequency? Those signals are going to have a return path that follows the trace so you’ll need to be careful with the ground plane by those traces, with vias to the ground plane by the trace. At high frequency, cross-talk between closely routed signal traces may become an issue. I seem to recall there were some good YT videos by Altium and Robert Lefranc (?? That doesn’t sound right but I can’t remember his surname but he will come up if you search for PCB layout.) having a ground plane on both inside layers helps because it minimises the distance between a trace and its return path (the pre-preg between layers 2 and 3 is relatively thick) Obviously there’s going to have to be some compromise given the power planes for the FPGA: if you could minimise their size and use traces on the top/bottom layer to reach them it might help. I’d say layout of those two components, with decoupling caps, are the most important on the board but I’m guessing you already know that.

I have no soldering advice for the BGA unfortunately. I guess a reflow oven would help. Alternatively, if your not fussed about practicing your soldering technique on that part, you might be able to get the board fabricator to do it if you can get the part to them.

Don’t forget that the FPGA (and possibly SRAM??) is likely to need a heatsink. I’d guess that will go on top so do the calcs and leave enough clearance and maybe even mechanical support.

RE: Scrutinize my FPGA PCB Layout

genebren — Tue, 12 Jul 2022 18:47:29 GMT

This looks very good so far. That is a very ambitious project that you are taking on there. The geometries are far beyond anything that I have attempted, not to mention the soldering job that you are looking at once you get the board. Good luck!

RE: Scrutinize my FPGA PCB Layout

cstanton — Tue, 12 Jul 2022 17:34:25 GMT

Is it a typical convention to use certain layers for particular functions? Such as layer 2 is the ground plane, 3 for power, etc.?