<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Lattice ECP5 FPGA architecture overview (part of OrangeCrab Dev Bd road-test)</title><link>/products/roadtest/b/blog/posts/lattice-ecp5-fpga-architecture-overview-part-of-orangecrab-dev-bd-road-test</link><description>Architecture overview 


 Lattice vision 


 PFU (Programmable Functional Unit) 


 Clocking 


 sysMEM Memory 


 sysDSP 


 PIO (programmable I/O cells) 


 Device configuration 


 SEU (Single Event Upset) 


 Links 

The following post gives an overview</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: Lattice ECP5 FPGA architecture overview (part of OrangeCrab Dev Bd road-test)</title><link>https://community.element14.com/products/roadtest/b/blog/posts/lattice-ecp5-fpga-architecture-overview-part-of-orangecrab-dev-bd-road-test</link><pubDate>Sat, 02 Oct 2021 17:41:47 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:525a0ad0-fe88-4c8b-88d7-4513ded66513</guid><dc:creator>DAB</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Nice post.&lt;/p&gt;&lt;p&gt;The architecture looks interesting.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;DAB&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=21971&amp;AppID=14&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>