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  • Author Author: doctorcdf
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XMOS xCORE-USB sliceKIT

doctorcdf

Table of contents

XMOS xCore-USB SliceKITThe xCORE-USB sliceKITxCORE-USB sliceKIT contains everything you need to start developing USB applications on xCORE multicore microcontrollers. The xCORE-USB sliceKITxCORE-USB sliceKIT features our 16 core High Speed USB device which delivers the deterministic, responsive processing required to handle a variety of peripheral interfaces, data processing and control tasks.
The kit includes the USB sliceCARD with USB A and USB B connectors which works with xCORE-USB integrated High Speed USB 2.0 PHY. Our sliceKIT product range includes a wide variety of other slice I/O cards, making it easy to rapidly develop systems.
Kit Contents
  • Core board with 16 core xCORE-USB multicore microcontroller
  • USB A/B sliceCARD
  • Mixed Signal sliceCARD
  • xTAG-2 debug adaptor
  • Power supply
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  • Testers will be selected on the basis of quality of applications: we expect a full and complete description of why you want to test this particular product.
  • Testers are required to produce a full, comprehensive and well thought out review within 2 months of receipt of the product.
  • Failure to provide this review within the above timescale will result in the enrolee being excluded from future RoadTests.
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  • I can't find xMOS processor maximum clock frequency. i know, it does say 1000MIPS, but i am more interested in MHz, since i know that my application need high real time computation power, and can't be disassembled to share computation with other cores. That means, if single core can't do computation in real time, it is a bad day for me

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  • I can't find xMOS processor maximum clock frequency. i know, it does say 1000MIPS, but i am more interested in MHz, since i know that my application need high real time computation power, and can't be disassembled to share computation with other cores. That means, if single core can't do computation in real time, it is a bad day for me

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  • in reply to Kilohercas

    Hi Linas,

     

    The clock is 500MHz, and there is a pipeline type structure (in this case 4 stages), meaning that the throughput will vary (e.g. due to pipeline stalls or intentionally due to instructions or I/O) depending on the actual instructions, and so the clock speed in MHz alone doesn't tell the entire story. As a result, if you're running computation only in a single core, the throughput will be anything from 125MIPS to 500MIPS, but 125MIPS will be guaranteed (500/4 = 125). This is under-using the device, since ideally you want to be using multiple XMOS cores, to get most use out of it. There are two separated tiles on the chip, which is how the 1000MIPS figure arises.