Lark Board - Altera Cyclone V SoC Evaluation Kit

Table of contents

Altera Lark BoardLark BoardLark Board is an evaluation board designed by Embest based on an Altera ARM (Cortex-A9 dual-core)+FPGA processor. The SoC, named 5CSXFC6D6F31 that comes from Cyclone V SX family, integrates not only the traditional FPGA fabric, but also an ARM Cortex-A9-based HPS (operating at 800MHz) and a high-speed transceiver (3Gbps Serdes) hard subsystem.
Lark BoardLark Board provides 1GB DDR3 SDRAM separately for both ARM and FPGA, and has 4 high-speed USB2.0 Host interfaces, a TF card slot for mass storage, a 12-bit camera interface, a VGA interface, a 24-bit LCD interface, PCIe, UART, JTAG, 3G bps SDI input/output and a HDMI interface. Additionally, two 2*200-pin connectors are mounted on the board in order to make the unused pins of HPS/FPGA available for users. Lark Board uses a switching power supply controller chip (integrated with inductor) that comes from Alteraís Enpirion family to provide a stable and efficient output for each BANK of FPGA. Meanwhile, it has two on-board DIP switches used to enable various voltage levels required by the different interfaces on the board with the purpose to facilitate power consumption evaluation conducted by users.
Lark BoardLark Board comes with a lot of FPGA example applications and the corresponding source code, Linux 3.10 and u-boot source code and Debian 7.4 system image, as well as schematics and key chipsí datasheets to help users implement evaluation and secondary development fast.
Features
  • Cyclone V SoC
  • On-board USB Blaster II
  • Supports VGA, LCD, SDI & HDMI
  • HPS Expansion
  • 4 x USB
  • PCIe
Webinar
Terms & Conditions
  • Testers will be selected on the basis of quality of applications: we expect a full and complete description of why you want to test this particular product.
  • Testers are required to produce a full, comprehensive and well thought out review within 2 months of receipt of the product.
  • Failure to provide this review within the above timescale will result in the enrolee being excluded from future RoadTests.
Reviews for this Roadtest
Comment List
Anonymous
  • Ok I am getting crazy, but here is another idea: https://embeddedmicro.com/tutorials/mojo/ This board uses and Arduino chip to program the FPGA. So the IDE is just Arduino based. If you have a spare UNO around, this maybe a solution to injecting a binary blob to the board. Here is the software used:

    Install The Software

    There are two programs you need to use when working the Mojo. The first is ISE. ISE is a program provided by Xilinx (the FPGA manufacture) that does the actual synthesis from text to a file you can load onto the board. The program is rather big and the download takes a while. Head over to the ISE Setup Tutorial and set it up.

    The next piece of software you need is the Mojo Loader. The Mojo Loader is a small program that takes the .bin file that is generated by ISE and sends it to your Mojo. It simply acts as the glue. Follow the Mojo Loader Tutorial to get that setup.

    I would think something like this could be cobbled together. Just my two cents worth of ideas.

  • Looking around I found this https://www.youtube.com/watch?v=aPXMkTJxD_s

    It has the same type of processor as the Lark board, but may be different as far as interfaces, etc. I like the explanation of interfacing with the FPGA. Maybe this can help you. Any thoughts?

    Clem

  • It's one of the 33 SDRAM registers, but HPS can also configure the FGPA/SDRAM connection along with the video controller and other hardware IC's.

     

    There was Linux but no hardware library for the hardware components of the board to work with that the board needed so I'm working on implementing USB communication through the Blaster II thingy with Visual Basic.net to talk with the hardware directly. So instead of setting up hardware during any boot up process other than bootROM, we'll be operating it all in real time in a sort of debug mode so SDRAM, SD Card etc will all work in real time.

     

    I might create an automated mode so once a program is loaded into SDRAM, maybe it can loop through the loaded program instead of waiting for data to come in through USB.

     

    In all, this is very advanced stuff, even the staff at the manufacturer couldn't help me out with the inquiry on how to write to the individual components of their board.

     

    The only person who would know would be the person who designed the circuit board, but there are no tech specs on the layout so it's just a matter of writing the registers in the correct sequence with the correct data for issuing commands to the controllers.

     

    Controlling the board from USB? yes, and once that occurs, there might not be a need for Eclipse or DS-5, and the app would probably work with all Cyclone V's at that point.

     

    I'll get the board working like a microcontroller in a way, even updating the FPGA fabric in real time.

  • This is very low level code if you have to program the SDRAM! If this is for the HPS, why this line:

    volatile const int *SDR_FPGA_Port_Reset = (volatile const int *)0xFFC25080; //32 bit 1 bitfields 14 bit

    Maybe the SDRAM is shared meaning it is dual ported? Anyhow I can see the misery for handling this detail. Is there Linux on the HSP part at least?

  • Here's how difficult this is without having a proper IDE or hardware library:

    And this is just for accessing HPS SDRAM, and I'm not sure which of the 2 HPS SDRAM chips this code is going to hit.

     

    33 registers just for SDRAM

     

    //HPS_SDRAM 0xFFC20000

    volatile const int *SDR_CTRLCFG = (volatile const int *)0xFFC25000; //32 bit 14 bitfields

    volatile const int *SDR_Dram_Timing1 = (volatile const int *)0xFFC25004; //32 bit 7 bitfields

    volatile const int *SDR_Dram_Timing2 = (volatile const int *)0xFFC25008; //32 bit 6 bitfields

    volatile const int *SDR_Dram_Timing3 = (volatile const int *)0xFFC2500C; //32 bit 6 bitfields

    volatile const int *SDR_Dram_Timing4 = (volatile const int *)0xFFC25010; //32 bit 4 bitfields

    volatile const int *SDR_Low_Power_Timing = (volatile const int *)0xFFC25014; //32 bit 2 bitfields

    volatile const int *SDR_Dram_ODT = (volatile const int *)0xFFC25018; //32 bit 2 bitfields

    volatile const int *SDR_Dram_AddrW = (volatile const int *)0xFFC2502C; //32 bit 4 bitfields

    volatile const int *SDR_Dram_Ifwidth = (volatile const int *)0xFFC25030; //32 bit 1 bitfield

    volatile const int *SDR_Dram_STS = (volatile const int *)0xFFC25038; //32 bit 5 bitfields

    volatile const int *SDR_Dram_INTR = (volatile const int *)0xFFC2503C; //32 bit 5 bitfields

    volatile const int *SDR_SBE_Count = (volatile const int *)0xFFC25040; //32 bit 1 bitfield

    volatile const int *SDR_DBE_Count = (volatile const int *)0xFFC25044; //32 bit 1 bitfield

    volatile const int *SDR_ERR_Addr = (volatile const int *)0xFFC25048; //32 bit 1 bitfields

    volatile const int *SDR_Drop_Count = (volatile const int *)0xFFC2504C; //32 bit 1 bitfield Address

    volatile const int *SDR_Drop_AddressT = (volatile const int *)0xFFC25050; //32 bit 1 bitfield CorrDropAddr

    volatile const int *SDR_Low_Power_Request = (volatile const int *)0xFFC25054; //32 bit 4 bitfields

    volatile const int *SDR_Low_Power_Rack = (volatile const int *)0xFFC25058; //32 bit 2 bitfields

    volatile const int *SDR_Static_CFG = (volatile const int *)0xFFC2505C; //32 bit 3 bitfields

    volatile const int *SDR_CTRL_Width = (volatile const int *)0xFFC25060; //32 bit 1 bitfields 2bit

    volatile const int *SDR_Port_CFG = (volatile const int *)0xFFC2507C; //32 bit 1 bitfields 10bit

    volatile const int *SDR_FPGA_Port_Reset = (volatile const int *)0xFFC25080; //32 bit 1 bitfields 14 bit

    volatile const int *SDR_Prot_Port_Default = (volatile const int *)0xFFC2508C; //32 bit 1 bitfields 10bit

    volatile const int *SDR_Prot_Rule_Addr = (volatile const int *)0xFFC25090; //32 bit 2 bitfields high/low address

    volatile const int *SDR_Prot_Rule_ID = (volatile const int *)0xFFC25094; //32 bit 2 bitfields high/low ID

    volatile const int *SDR_Prot_Rule_Data = (volatile const int *)0xFFC25098; //32 bit 4 bitfields

    volatile const int *SDR_Prot_Rule_RdWr = (volatile const int *)0xFFC2509C; //32 bit 3 bitfields

    volatile const int *SDR_MP_Priority = (volatile const int *)0xFFC250AC; //32 bit 1 bitfield 30bit

    volatile const int *SDR_Remap_Priority = (volatile const int *)0xFFC250E0; //32 bit 1 bitfield 8bit

    volatile const int *SDR_MPweight_0_4 = (volatile const int *)0xFFC250B0; //32 bit 1 bitfields 32bit staticweight_31_0

    volatile const int *SDR_MPweight_1_4 = (volatile const int *)0xFFC250B4; //32 bit 2 bitfields 32bit

    volatile const int *SDR_MPweight_2_4 = (volatile const int *)0xFFC250B8; //32 bit 1 bitfields 32bit sumofweights_45_14

    volatile const int *SDR_MPweight_3_4 = (volatile const int *)0xFFC250BC; //32 bit 1 bitfields 18bit sumofweights_63_46

  • My application for the road test included programming the hardware components on the Lark Board in binary mode to compare the performance of the peripherals running in a Linux mode. There was only one problem I encountered so far, no way to program the board with an IDE was given, and there was no board-specific hardware library to support the features of the board included with the kit.

     

    They did however hand other peoples' hardware libraries dating back from 1992-2010 for hardware the Lark Board doesn't even use, like dial up modem, IDE, SATA. 50,000 bogus hardware devices.

     

    They should have included a proper library, such that it included SDRAM.h, HPS.h, FPGA.h, SDI.h, QSPI.h, PLL.h and so on specific to the board hardware, not technology from the 1990's.

     

    I haven't placed a review in yet because I still have faith this board can be programmed in binary mode without a board-specific library to support the hardware.

    I resorted to creating a brand new compiler, and am 50% finished entering in all the hardware addresses from the memory map for communicating with the hardware directly.

     

    They should create an Embest Studio for development on their boards like Atmel Studio has for theirs. I don't see a point why an $800 board is running free software. Potential users of the board will be wanting full control over the board so they can program it the way they want. They won't be wanting to use Linux, but as developers, they'll be wanting to program the hardware the way they want so it can suit their needs for their applications.

     

    Embest needs to create an Embest Studio to support their boards like Atmel Studio does for their line of boards. Users can select the board they want to program for, and they even have examples of the hardware features per component. I did not see any of this type of support with this kit.

     

    No IDE, No hardware library, just a bunch of source code for technology that existed 10-20 years ago. What can you expect for a board made in China.

  • @

    Wow! I was considering to apply for this and kinda glad I did not. I did not have experience with FPGA (wishing I will sometime in future), The board had too much to worry about for interfaces. Lastly, the webinar did not leave me with any good purpose in mind. My I ask what your proposal is/was? I would not be surprised if it changes. If I have any ideas, would you like to hear? Maybe a group effort can be beneficial. But that is up to you. Thanks for the updates and progress. You certainly did more research than I had done.

     

    Wishing you the best,

    Clem

  • Hi Jason,

     

    The Cortex-A portion of this board is an applications processor, it will be very rare for anyone to want to go OS-less (i.e. bare metal) with this. It would be extremely disappointing, because you'd no longer have the ability to use a ton of libraries and applications that already exist for popular OS's, i.e. one could spend years reinventing the wheel, just to draw some lines on a screen for example. it's not that they don't want people to program the boards! That would make no sense.

     

    To make maximum use of it, an OS needs to be used - most likely Linux but others (usually paid options) are possible too. Is there no Linux image available or supplied for this? (The text in the post says there is Debian - which sounds ideal to get started). If not, then one will need to be built. The image can then contain a compiler for you to then develop your programs to run inside the OS - the A9 should be powerful enough for you to develop apps directly using the A9 itself for compilation.

     

    All the above refers to just the Cortex-A portion - for the FPGA portion, it is near-mandatory to use the Xilinx tools because there is no other option - this is just the way it is currently.

  • Does it need a specific IDE? Or is there a GCC toolchain?

  • Hang tight everyone, none of the Altera software is working on any of my machines so I'm in the middle of building a binary compiler for the Cyclone V and a board specific library to support all the features of each component of the board for bare metal and user space application development.

     

    For people interested in the board, be prepared to program it in 100% binary machine language. There's no other way around it without an operational development environment the manufacturer should have created and supplied for use with their board.