Lark Board - Altera Cyclone V SoC Evaluation Kit

Table of contents

Altera Lark BoardLark BoardLark Board is an evaluation board designed by Embest based on an Altera ARM (Cortex-A9 dual-core)+FPGA processor. The SoC, named 5CSXFC6D6F31 that comes from Cyclone V SX family, integrates not only the traditional FPGA fabric, but also an ARM Cortex-A9-based HPS (operating at 800MHz) and a high-speed transceiver (3Gbps Serdes) hard subsystem.
Lark BoardLark Board provides 1GB DDR3 SDRAM separately for both ARM and FPGA, and has 4 high-speed USB2.0 Host interfaces, a TF card slot for mass storage, a 12-bit camera interface, a VGA interface, a 24-bit LCD interface, PCIe, UART, JTAG, 3G bps SDI input/output and a HDMI interface. Additionally, two 2*200-pin connectors are mounted on the board in order to make the unused pins of HPS/FPGA available for users. Lark Board uses a switching power supply controller chip (integrated with inductor) that comes from Alteraís Enpirion family to provide a stable and efficient output for each BANK of FPGA. Meanwhile, it has two on-board DIP switches used to enable various voltage levels required by the different interfaces on the board with the purpose to facilitate power consumption evaluation conducted by users.
Lark BoardLark Board comes with a lot of FPGA example applications and the corresponding source code, Linux 3.10 and u-boot source code and Debian 7.4 system image, as well as schematics and key chipsí datasheets to help users implement evaluation and secondary development fast.
Features
  • Cyclone V SoC
  • On-board USB Blaster II
  • Supports VGA, LCD, SDI & HDMI
  • HPS Expansion
  • 4 x USB
  • PCIe
Webinar
Terms & Conditions
  • Testers will be selected on the basis of quality of applications: we expect a full and complete description of why you want to test this particular product.
  • Testers are required to produce a full, comprehensive and well thought out review within 2 months of receipt of the product.
  • Failure to provide this review within the above timescale will result in the enrolee being excluded from future RoadTests.
Comment List
Anonymous
Parents
  • This is very low level code if you have to program the SDRAM! If this is for the HPS, why this line:

    volatile const int *SDR_FPGA_Port_Reset = (volatile const int *)0xFFC25080; //32 bit 1 bitfields 14 bit

    Maybe the SDRAM is shared meaning it is dual ported? Anyhow I can see the misery for handling this detail. Is there Linux on the HSP part at least?

Comment
  • This is very low level code if you have to program the SDRAM! If this is for the HPS, why this line:

    volatile const int *SDR_FPGA_Port_Reset = (volatile const int *)0xFFC25080; //32 bit 1 bitfields 14 bit

    Maybe the SDRAM is shared meaning it is dual ported? Anyhow I can see the misery for handling this detail. Is there Linux on the HSP part at least?

Children
  • It's one of the 33 SDRAM registers, but HPS can also configure the FGPA/SDRAM connection along with the video controller and other hardware IC's.

     

    There was Linux but no hardware library for the hardware components of the board to work with that the board needed so I'm working on implementing USB communication through the Blaster II thingy with Visual Basic.net to talk with the hardware directly. So instead of setting up hardware during any boot up process other than bootROM, we'll be operating it all in real time in a sort of debug mode so SDRAM, SD Card etc will all work in real time.

     

    I might create an automated mode so once a program is loaded into SDRAM, maybe it can loop through the loaded program instead of waiting for data to come in through USB.

     

    In all, this is very advanced stuff, even the staff at the manufacturer couldn't help me out with the inquiry on how to write to the individual components of their board.

     

    The only person who would know would be the person who designed the circuit board, but there are no tech specs on the layout so it's just a matter of writing the registers in the correct sequence with the correct data for issuing commands to the controllers.

     

    Controlling the board from USB? yes, and once that occurs, there might not be a need for Eclipse or DS-5, and the app would probably work with all Cyclone V's at that point.

     

    I'll get the board working like a microcontroller in a way, even updating the FPGA fabric in real time.