Lark Board - Altera Cyclone V SoC Evaluation Kit

Table of contents

Altera Lark BoardLark BoardLark Board is an evaluation board designed by Embest based on an Altera ARM (Cortex-A9 dual-core)+FPGA processor. The SoC, named 5CSXFC6D6F31 that comes from Cyclone V SX family, integrates not only the traditional FPGA fabric, but also an ARM Cortex-A9-based HPS (operating at 800MHz) and a high-speed transceiver (3Gbps Serdes) hard subsystem.
Lark BoardLark Board provides 1GB DDR3 SDRAM separately for both ARM and FPGA, and has 4 high-speed USB2.0 Host interfaces, a TF card slot for mass storage, a 12-bit camera interface, a VGA interface, a 24-bit LCD interface, PCIe, UART, JTAG, 3G bps SDI input/output and a HDMI interface. Additionally, two 2*200-pin connectors are mounted on the board in order to make the unused pins of HPS/FPGA available for users. Lark Board uses a switching power supply controller chip (integrated with inductor) that comes from Alteraís Enpirion family to provide a stable and efficient output for each BANK of FPGA. Meanwhile, it has two on-board DIP switches used to enable various voltage levels required by the different interfaces on the board with the purpose to facilitate power consumption evaluation conducted by users.
Lark BoardLark Board comes with a lot of FPGA example applications and the corresponding source code, Linux 3.10 and u-boot source code and Debian 7.4 system image, as well as schematics and key chipsí datasheets to help users implement evaluation and secondary development fast.
Features
  • Cyclone V SoC
  • On-board USB Blaster II
  • Supports VGA, LCD, SDI & HDMI
  • HPS Expansion
  • 4 x USB
  • PCIe
Webinar
Terms & Conditions
  • Testers will be selected on the basis of quality of applications: we expect a full and complete description of why you want to test this particular product.
  • Testers are required to produce a full, comprehensive and well thought out review within 2 months of receipt of the product.
  • Failure to provide this review within the above timescale will result in the enrolee being excluded from future RoadTests.
Comment List
Anonymous
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  • @

    Wow! I was considering to apply for this and kinda glad I did not. I did not have experience with FPGA (wishing I will sometime in future), The board had too much to worry about for interfaces. Lastly, the webinar did not leave me with any good purpose in mind. My I ask what your proposal is/was? I would not be surprised if it changes. If I have any ideas, would you like to hear? Maybe a group effort can be beneficial. But that is up to you. Thanks for the updates and progress. You certainly did more research than I had done.

     

    Wishing you the best,

    Clem

  • Here's how difficult this is without having a proper IDE or hardware library:

    And this is just for accessing HPS SDRAM, and I'm not sure which of the 2 HPS SDRAM chips this code is going to hit.

     

    33 registers just for SDRAM

     

    //HPS_SDRAM 0xFFC20000

    volatile const int *SDR_CTRLCFG = (volatile const int *)0xFFC25000; //32 bit 14 bitfields

    volatile const int *SDR_Dram_Timing1 = (volatile const int *)0xFFC25004; //32 bit 7 bitfields

    volatile const int *SDR_Dram_Timing2 = (volatile const int *)0xFFC25008; //32 bit 6 bitfields

    volatile const int *SDR_Dram_Timing3 = (volatile const int *)0xFFC2500C; //32 bit 6 bitfields

    volatile const int *SDR_Dram_Timing4 = (volatile const int *)0xFFC25010; //32 bit 4 bitfields

    volatile const int *SDR_Low_Power_Timing = (volatile const int *)0xFFC25014; //32 bit 2 bitfields

    volatile const int *SDR_Dram_ODT = (volatile const int *)0xFFC25018; //32 bit 2 bitfields

    volatile const int *SDR_Dram_AddrW = (volatile const int *)0xFFC2502C; //32 bit 4 bitfields

    volatile const int *SDR_Dram_Ifwidth = (volatile const int *)0xFFC25030; //32 bit 1 bitfield

    volatile const int *SDR_Dram_STS = (volatile const int *)0xFFC25038; //32 bit 5 bitfields

    volatile const int *SDR_Dram_INTR = (volatile const int *)0xFFC2503C; //32 bit 5 bitfields

    volatile const int *SDR_SBE_Count = (volatile const int *)0xFFC25040; //32 bit 1 bitfield

    volatile const int *SDR_DBE_Count = (volatile const int *)0xFFC25044; //32 bit 1 bitfield

    volatile const int *SDR_ERR_Addr = (volatile const int *)0xFFC25048; //32 bit 1 bitfields

    volatile const int *SDR_Drop_Count = (volatile const int *)0xFFC2504C; //32 bit 1 bitfield Address

    volatile const int *SDR_Drop_AddressT = (volatile const int *)0xFFC25050; //32 bit 1 bitfield CorrDropAddr

    volatile const int *SDR_Low_Power_Request = (volatile const int *)0xFFC25054; //32 bit 4 bitfields

    volatile const int *SDR_Low_Power_Rack = (volatile const int *)0xFFC25058; //32 bit 2 bitfields

    volatile const int *SDR_Static_CFG = (volatile const int *)0xFFC2505C; //32 bit 3 bitfields

    volatile const int *SDR_CTRL_Width = (volatile const int *)0xFFC25060; //32 bit 1 bitfields 2bit

    volatile const int *SDR_Port_CFG = (volatile const int *)0xFFC2507C; //32 bit 1 bitfields 10bit

    volatile const int *SDR_FPGA_Port_Reset = (volatile const int *)0xFFC25080; //32 bit 1 bitfields 14 bit

    volatile const int *SDR_Prot_Port_Default = (volatile const int *)0xFFC2508C; //32 bit 1 bitfields 10bit

    volatile const int *SDR_Prot_Rule_Addr = (volatile const int *)0xFFC25090; //32 bit 2 bitfields high/low address

    volatile const int *SDR_Prot_Rule_ID = (volatile const int *)0xFFC25094; //32 bit 2 bitfields high/low ID

    volatile const int *SDR_Prot_Rule_Data = (volatile const int *)0xFFC25098; //32 bit 4 bitfields

    volatile const int *SDR_Prot_Rule_RdWr = (volatile const int *)0xFFC2509C; //32 bit 3 bitfields

    volatile const int *SDR_MP_Priority = (volatile const int *)0xFFC250AC; //32 bit 1 bitfield 30bit

    volatile const int *SDR_Remap_Priority = (volatile const int *)0xFFC250E0; //32 bit 1 bitfield 8bit

    volatile const int *SDR_MPweight_0_4 = (volatile const int *)0xFFC250B0; //32 bit 1 bitfields 32bit staticweight_31_0

    volatile const int *SDR_MPweight_1_4 = (volatile const int *)0xFFC250B4; //32 bit 2 bitfields 32bit

    volatile const int *SDR_MPweight_2_4 = (volatile const int *)0xFFC250B8; //32 bit 1 bitfields 32bit sumofweights_45_14

    volatile const int *SDR_MPweight_3_4 = (volatile const int *)0xFFC250BC; //32 bit 1 bitfields 18bit sumofweights_63_46

Comment
  • Here's how difficult this is without having a proper IDE or hardware library:

    And this is just for accessing HPS SDRAM, and I'm not sure which of the 2 HPS SDRAM chips this code is going to hit.

     

    33 registers just for SDRAM

     

    //HPS_SDRAM 0xFFC20000

    volatile const int *SDR_CTRLCFG = (volatile const int *)0xFFC25000; //32 bit 14 bitfields

    volatile const int *SDR_Dram_Timing1 = (volatile const int *)0xFFC25004; //32 bit 7 bitfields

    volatile const int *SDR_Dram_Timing2 = (volatile const int *)0xFFC25008; //32 bit 6 bitfields

    volatile const int *SDR_Dram_Timing3 = (volatile const int *)0xFFC2500C; //32 bit 6 bitfields

    volatile const int *SDR_Dram_Timing4 = (volatile const int *)0xFFC25010; //32 bit 4 bitfields

    volatile const int *SDR_Low_Power_Timing = (volatile const int *)0xFFC25014; //32 bit 2 bitfields

    volatile const int *SDR_Dram_ODT = (volatile const int *)0xFFC25018; //32 bit 2 bitfields

    volatile const int *SDR_Dram_AddrW = (volatile const int *)0xFFC2502C; //32 bit 4 bitfields

    volatile const int *SDR_Dram_Ifwidth = (volatile const int *)0xFFC25030; //32 bit 1 bitfield

    volatile const int *SDR_Dram_STS = (volatile const int *)0xFFC25038; //32 bit 5 bitfields

    volatile const int *SDR_Dram_INTR = (volatile const int *)0xFFC2503C; //32 bit 5 bitfields

    volatile const int *SDR_SBE_Count = (volatile const int *)0xFFC25040; //32 bit 1 bitfield

    volatile const int *SDR_DBE_Count = (volatile const int *)0xFFC25044; //32 bit 1 bitfield

    volatile const int *SDR_ERR_Addr = (volatile const int *)0xFFC25048; //32 bit 1 bitfields

    volatile const int *SDR_Drop_Count = (volatile const int *)0xFFC2504C; //32 bit 1 bitfield Address

    volatile const int *SDR_Drop_AddressT = (volatile const int *)0xFFC25050; //32 bit 1 bitfield CorrDropAddr

    volatile const int *SDR_Low_Power_Request = (volatile const int *)0xFFC25054; //32 bit 4 bitfields

    volatile const int *SDR_Low_Power_Rack = (volatile const int *)0xFFC25058; //32 bit 2 bitfields

    volatile const int *SDR_Static_CFG = (volatile const int *)0xFFC2505C; //32 bit 3 bitfields

    volatile const int *SDR_CTRL_Width = (volatile const int *)0xFFC25060; //32 bit 1 bitfields 2bit

    volatile const int *SDR_Port_CFG = (volatile const int *)0xFFC2507C; //32 bit 1 bitfields 10bit

    volatile const int *SDR_FPGA_Port_Reset = (volatile const int *)0xFFC25080; //32 bit 1 bitfields 14 bit

    volatile const int *SDR_Prot_Port_Default = (volatile const int *)0xFFC2508C; //32 bit 1 bitfields 10bit

    volatile const int *SDR_Prot_Rule_Addr = (volatile const int *)0xFFC25090; //32 bit 2 bitfields high/low address

    volatile const int *SDR_Prot_Rule_ID = (volatile const int *)0xFFC25094; //32 bit 2 bitfields high/low ID

    volatile const int *SDR_Prot_Rule_Data = (volatile const int *)0xFFC25098; //32 bit 4 bitfields

    volatile const int *SDR_Prot_Rule_RdWr = (volatile const int *)0xFFC2509C; //32 bit 3 bitfields

    volatile const int *SDR_MP_Priority = (volatile const int *)0xFFC250AC; //32 bit 1 bitfield 30bit

    volatile const int *SDR_Remap_Priority = (volatile const int *)0xFFC250E0; //32 bit 1 bitfield 8bit

    volatile const int *SDR_MPweight_0_4 = (volatile const int *)0xFFC250B0; //32 bit 1 bitfields 32bit staticweight_31_0

    volatile const int *SDR_MPweight_1_4 = (volatile const int *)0xFFC250B4; //32 bit 2 bitfields 32bit

    volatile const int *SDR_MPweight_2_4 = (volatile const int *)0xFFC250B8; //32 bit 1 bitfields 32bit sumofweights_45_14

    volatile const int *SDR_MPweight_3_4 = (volatile const int *)0xFFC250BC; //32 bit 1 bitfields 18bit sumofweights_63_46

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