Terasic P0082 DE0-Nano FPGA Development Kit

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The P0082 is a DE0-Nano Development board is a compact-sized FPGA development platform suited for prototyping circuit designs such as robots and "portable" projects. The board is designed to be used in the simplest possible implementation targeting the Cyclone IV device up to 22,320 logic elements (LEs).


It allows user to extend designs beyond the DE0-Nano board with two external general-purpose I/O (GPIO) headers. It allows users to handle larger data storage and frame buffering with on-board memory devices including SDRAM and EEPROM. It provides enhanced user peripheral with LEDs and push buttons.


Other Features

  • Cyclone IV EP4CE22F17C6N FPGA
  • Configuration & set-up elements: On-Board USB Blaster ckt, serial configuration device EPCS16
  • Memory devices:32MB SDRAM,2Kb I2C EEPROM
  • G-sensor includes ADI ADXL345, 3-axis accelerometer with high resolution (13bits)
  • 8-channel, 12bit Analogue to digital converter
  • On-Board 50MHz clock oscillator
  • Altera complete design suite
  • Features DE0-Nano quick start guide
  • USB Mini-B cable
  • Reconfigurable without requiring superfluous hardware,
  • Suitable for mobile designs where portable power is crucial
  • Provides three power scheme options including a USB Mini-AB port, 2 pin external power header and two DC 5-V pins.


Important Dates

Enrollment Begins: June 2 2017

Enrollment Ends: July 19 2017

RoadTesters Selected: July 19 2017

Product Shipped: July 20 2017

RoadTesting Begins: July 27 2017

Reminder/Update Email: TBD*

Submit Reviews By: Sept 25 2017**


*The element14 RoadTest Staff will send this reminder/update email.

**If a RoadTester is unable to meet the deadline, please notify the RoadTest Program Lead, , as soon as possible before the deadline.


The following applicants were selected as official RoadTesters:


Terms & Conditions

Terasic P0082 DE0-Nano FPGA Development Kit – RoadTest

Terms and Conditions

These are the terms and conditions which govern theTerasic P0082 DE0-Nano FPGA Development Kit RoadTest contest. This Contest requires participants to submit an application indicating their previous experience with this type of equipment/component, information on what they would do to test the equipment/component, and the applicant’s desire to post a thorough review of their experience with images, photos, or other supplemental materials. Participants will be required to meet the Conditions for Participation.  The winners of this RoadTest will receive the item(s) listed below. RoadTest Reviews are due no later than 60 days after the receipt of the item(s). No other prizes are offered.

The Principal terms of the Competition:

The following words and phrases are used in these terms and conditions and have the meanings given to them below.

Terasic P0082 DE0-Nano FPGA Development Kit

(RoadTest or Contest)

Key dates:

Applications Close: midnight (GMT) on July 19  2017

Announcement of Winner (estimated): July 26 2017


Prize:  Terasic P0082 DE0-Nano FPGA Development Kit

Additional Prizes: none

Competition Site: https://www.element14.com/community/groups/roadtest?ICID=menubar_resources_roadtest

Site or element14 Community: www.element14.com/community

Judges: members of the element14 community team chosen at the Organiser’s discretion.

Judging Criteria, All of the following which will have equal weighting:

· Demonstrated competence with the technologies including links or descriptions of past projects

· Qualifications as indicated by current job role and/or schooling/vocational training;

· A thorough description of how the prize would be tested;

· Likelihood that the Applicant will blog about the prize and provide a review on element14.com;

· Originality;

· Innovation.

Organiser: Premier Farnell plc (registered in England and Wales under company number 876412) whose registered office is at Farnell House, Forge Lane, Leeds, UK

Conditions for Qualification: in addition to meeting the requirements of these terms, all persons applying to take part in the Contest (each one an Applicant) must:

· Provide a RoadTest application describing what he/she would do if awarded the Prize including similar previous projects, product experience and qualifications

Terms: these terms and conditions which govern the Competition and to which the Organiser reserves the right to make changes from time to time and the latest version of these Terms from time to time will be posted to the Site.

  1. Eligibility
  2. Applications:
  3. Selecting Winners:   
  4. Liability:
  5. General:

1.1 Save as set out in these Terms, the Contest is open to any natural or legal person, firm or company or group of natural persons or unincorporated body.

1.2 All Applicants must be aged at least 18 at the time of their application.

1.3 Applicants must not enter the RoadTest if doing so or taking part may:

1.3.1 cause the Organiser and/or themselves to be in breach of any agreement (including but not limited to any contract of employment) to which they are a party or in breach of any law, regulation or rule having the force of law to which the Organiser or the Applicant may be subject or any policy of the Organiser or the Sponsor;

1.3.2 Require the Organiser to obtain any licence, authorisation or permission to deal with the Applicant; or

1.3.3 Be in breach of any policy or practice of their employer. Some employers prohibit or restrict their employees from taking part in competitions such as these or receiving prizes under them and the Organiser respects those policies and practices.

The Organiser reserves the right to disqualify any Application made in breach of these Terms and to reject any Application which it reasonably believes may be or become in breach. The Organiser reserves the right to require evidence in such form as the Organiser may reasonably require of any Applicant’s compliance with any of these Terms and to disqualify any Applicant or Participant who cannot provide such evidence reasonably promptly. 

1.4 Multiple applications are not permitted.

1.5 Applications may not be submitted by an agent whether acting on behalf of an undisclosed principal or otherwise.

1.6 The Contest is NOT open to:

1.6.1 Any person or entity who is a resident or national of any country which is subject to sanctions, embargoes or national trade restrictions of the United States of America, the European Union or the United Kingdom;

1.6.2 Any employee, director, member, shareholder (as appropriate) or any of their direct families (parents, siblings, spouse, partner, children) (“Direct Families”) of the Organiser and Sponsors; or

2.1 Each Applicant must fully complete and submit a RoadTest Application by the Application Close.

2.2 By submitting a Registration Form, each Applicant:

2.2.1 Authorises the Organiser to use his or her personal data (as defined in the Data Protection Act 1998) for the purposes of running and promoting the RoadTest;

2.2.2 Authorises the Organizer to copy, reproduce and publish their application should they be accepted as a Participant;

2.2.3 Will be deemed to have read, accepted and agree to be bound by these Terms. Applicants are advised to print and keep safe these Terms;

2.2.4 Authorises the Organiser to copy, reproduce and use the Application and/or Review for the purposes of the RoadTest and as otherwise contemplated by these Terms. The Organiser will not be responsible for any inaccuracy, error or omission contained in any reproduction or use of the Project Blogs.

2.2.5 Licenses the Organiser to use the intellectual property in the Project (IP) for the purposes of this Contest. As between the Applicant and the Organiser the IP remains owned by the Applicant.

2.2.6 Grants the Organiser the right to use his or her likeness, photographs, logos, trademarks, audio or video recordings without restriction for the purposes of Contest or the promotion of it or the Site;

2.2.7 Agrees to participate positively in all publicity surrounding the Contest;

2.2.8 Agrees to be responsible for all expenses and costs incurred by him or her in preparing for, entering and participating in the Contest (save for any expenses expressly agreed by the Organiser to be borne by it in these Terms);

2.2.9 Confirms that he or she owns all IP used in his or her application or Project or Blogs and indemnifies the Organiser from any claim by a third party that use of any material provided by an Applicant to the Organiser infringes the intellectual property rights of any third party;

2.2.10 Agrees not to act in any way or fail to act in any way or be associated with any cause or group which would have a negative impact on the reputation of the Organiser and/or the RoadTest.

2.3 All applications submitted to this RoadTest must meet the following criteria:

2.3.1 Applicants must be the author, creator and owner of the proposed review idea. Applicants must not submit someone else’s idea;

2.3.2 The proposed application must be reasonably achievable by the within the time constraints of the Contest; 

2.3.3 Applications must not include or propose any of the following, the inclusion of which shall render any proposed application ineligible:

(a) Applications which relate to socially taboo topics, such as illicit drug use or sexual gratification;

(b) Applications that are or could reasonably be considered to be illegal, immoral, discriminatory or offensive as determined by the Organiser;

(c) Applications in relation to them which if accepted would infringe or breach any of the policies or terms of access or use of the Site.

2.4 No Application may contain any of the hazardous substances identified by Article 4 of Directive 2002/95/EC of the European Parliament on the Restrictions on the Use of Substances in Electronic and Electrical Equipment ("the Directive") or the use of such hazardous substances in the in any such Project must not exceed the maximum concentration values set out in the Directive.

3.1 Winners will be selected by the Organiser on the basis of the quality of his or her application and its adherence to these Terms.

3.2 The total number of Winners selected will be at least the minimum number set out above but the actual number is at the sole discretion of the Organizer and/or the Sponsor, if applicable.

3.3 The Organiser will use all reasonable efforts to announce the Winners via an update to the RoadTest page by the date listed above.

3.4 Winners agree to take part in all publicity which the Organiser or the Sponsor wishes to use to promote the RoadTest, the Products featured or other Contests with which the Organiser may be connected from time to time.

3.5 Details of the Winners may also be published in the media.

3.6 Winners are responsible for all applicable taxes, duties or other charges payable in relation to any prize.


4.1 The Organiser hereby excludes all and any Liability arising out of the Contest or the acceptance, use, quality, condition, suitability or performance of any Prize, even where that Liability may arise from the Organiser’s negligence.

4.2 Nothing in these Terms will affect any Liability of the Organiser for death or personal injury arising from its negligence, for breach of Part II of the Consumer Protection Act 1987 (in the event that any entrant is entitled to claim rights under the Consumer Protection Act 1987) or for any matter in relation to which it would be illegal for the Organiser to exclude or to attempt to exclude its Liability.

4.3 Subject to 4.2, neither the Organiser, any parent company nor any subsidiary of the Organiser or such parent company or any of their directors, officers and employees (together referred to in these terms and the ‘Associates’) makes any guarantee, warranty or representation of any kind, express or implied, with respect to this Competition or the Prizes potentially available under it. Neither the Organiser nor any of its Associates shall be responsible for any Liability that may arise out of or in connection with person’s participation in this Competition, the claiming, redemption or value of any prizes under it, the use or enjoyment of such prizes or any events or circumstances arising out of or in connection with any of them. Any implied warranties of condition, merchantability or suitability or fitness for purpose of any of them are hereby expressly excluded. Wherever used in these Terms, ‘Liability’ shall mean any and all costs, expenses, claims, damages, actions, proceedings, demands, losses and other liabilities (including legal fees and costs on a full indemnity basis) arising directly or indirectly out of or in connection with the matter concerned. 

5.1 The RoadTest is organised and sponsored by the Organiser. The Organiser reserves the right to delegate all or any of its powers, rights and obligations arising in relation to the RoadTest to any Associate and certain such rights and powers are assumed by the Organiser on behalf of itself and each Associate. Reference to “Organiser” shall be deemed to include reference to each Associate.

5.2 The RoadTest may be terminated at any time if there are, in the sole opinion of the Organiser, an insufficient number of entries, or if the Applications are not of an appropriate standard for a competition of this nature. The Organiser has the right to cancel or suspend the RoadTest at any time due to circumstances outside its reasonable control.

5.3 The Organiser shall have the sole discretion to disqualify (without correspondence or right of appeal) any Applicant it considers to be adversely affecting the process or the operation of the RoadTest or to be in breach of these Terms or to be acting in a disruptive manner or with intent to annoy, abuse, threaten or harass any other Applicant or Participant.

5.4 The Organiser has the right to amend or add to these Terms from time to time. Revised Terms and Conditions will be posted on the Contest Site and it is a condition of entry to the RoadTest that Applicants agree to comply with these Terms and, if appropriate, such Terms as amended from time to time.

5.5 Headings are for convenience only and do not affect the interpretation or construction of these Terms and Conditions.

5.6 These Terms and the operation of the Contest shall be governed by and construed in accordance with English Law and any claim or matter arising under these Terms shall be subject to the exclusive jurisdiction of the English courts.

Reviews for this Roadtest
Comment List

Top Comments

Parents Comment Children
  • ,


    I see your point about the PsOC v FPGA.


    Here is is how I am approaching the FPGA v PSoC v Microcontroller platform choice:


    There are several ways to tackle an embedded system problem ranging from heavily software, or firmware, oriented, through to heavily hardware oriented.  On the heavily firmware oriented end of the spectrum a designer could use a highly integrated microcontroller and solve the task at hand using code. On the heavily hardware end of the spectrum, a designer could use an FPGA and VHDL, or schematic capture, to render a logic gate solution.  In between I see the PSoC platform as an adjustable blend of hardware and firmware.


    My experience in working with each of these approaches has led me to believe that each is appropriate for achieving specific outcomes.  FPGA works well when speed is of paramount concern (although modern microcontrollers are getting pretty zippy).  Microcontrollers are great for rapid development and where low cost and flexibility are important.  The PSoC platform to me sits in between and can serve both masters.


    I have experiential bias grown from many years of developing Microcontroller based solutions and writing huge volumes of embedded code.  This bias makes me prefer microcontrollers and the PSoC platform when compared to FPGAs. All of the problems I have needed to address could be solved with microcontrollers or PSoCs.  I need to get more FPGA experience to develop a more informed perspective.  My previous experience with an FPGA evaluation kit 10 years ago left me thinking they required too much advanced knowledge to be of much use to hobbyists.  They seemed to be relegated to engineering level application only.  However, I am going to assume the tools have advanced over the last 10 years since my first exposure to FPGAs.


    The random pattern RGB LED controller mentioned previously has been fully developed using firmware on a PIC microcontroller and fully developed on a PSoC 4.  I would like to develop the same functionality on the TerASIC FPGA mostly to gauge the difficulty in doing so compared to the PIC and PSoC.  The LED controller will not strain the capabilities of the FPGA even a little bit.  My Road Test would evaluate the difficulty of using the platform to solve a known solvable problem using other common platforms.


    Mark A.

  • Hi Jan,


    I agree.

    In many ways they are apples and oranges.

    I brought up the comparison issue due to the basic capability in the PSOC to actually do a little FPGA using their high level components.


    The Neo looks like it has the full low level component connection capability which would be very intriguing for the right type of hardware project.


    There is a lot of potential there, but I am dubious if a new maker can really exploit that capability easily.



  • DAB, this is just what I want to see if possible. I suppose that they have done something better than what we are expecting by a "normal" FPGA just to put things easier to be done. We should not forget that the assertion "will PSoC (Cypress in detail) be the Arduino killing?" revealed totally false just for the difficult in programming it respect to the Arduino. So, we are some clear markers defining the difficulty levels. And first of all it is interesting to place this product in the - hopefully - right position respect his counterparts.



  • Starting from something you've already done is good, but I'd expand it a bit in order to make it appeal to TerASIC (and get you chosen for the roadtest). According to their product page, they are aiming the board at development use (as in hardware product development) or education. So, starting from where you are, I think I'd take what you've done and make a simple 'product' out of it which you can then 'develop' with aid of the board.


    FPGAs like this incorporate very fast on-board RAM that's very easy to use. So what you could do is allocate some of the RAM for a frame buffer. Some simple counters to address the store, the output circuit you've already developed, and you then have something that will push the store contents out to the LED strip. Duplicating your output circuit is easy, so you could have multiple strips running from the same memory (the logic and RAM are fast enough that they could easily service multiple strips). On the other side of the store (you can normally choose for it to be dual-port, so you don't even need to worry about how to multiplex addresses and deal with clashes, etc), maybe you could implement an SPI interface which would make it fairly universal and usable with almost any SBC [to the SBC, and the programmer, the LED array would then just look like an SPI memory]. That might seem like a lot, but you can see how it builds up in stages, with each section testable before you move to the next, and once you get into it and can use the tools you'll find it builds quickly. It's particularly nice working with LEDs, because you get to (literally) see what's going on and when things aren't working as they should - particularly if you start at the end and work backwards. I think that once you did get into the flow of it, you wouldn't want to stop and would actually develop it beyond what I've outlined here (because you'd keep thinking of new ideas and would want to try them out).


    Anyway - just an idea - you might want to go in a different direction or stick with what you're doing at the moment. I just feel that they're more likely to go for something like this than a straight comparison with a PSoC (which would be more of a PSoC roadtest than a TerASIC one).


    If you want a second opinion [or should I say first opinion, since we all seem to be numbering from #0 these days - thank you Phil!] on the practicalities of this, either or ought to be able to help [I've got the impression from things each of them has written that they've both worked with logic like this]. Mustn't forget too. Don't know about some of the others.


    BTW Microcontrollers may be getting pretty zippy, but they're not zippy in the way that this FPGA is zippy. This has got 66 multipliers that can run at up to 280MHz. That's over 18 billion multiplies a second (which is really nifty if you want to do some signal processing).

  • Jon,


    I like your suggestions.

    May as well throttle up the project to take advantage of the FPGA platform.


    Just not sure I could get it all done in a two month window of working evenings and weekends.


    Perhaps a reasonable scope of work can be devised that highlights FPGA advantages without consuming every waking hour.  The ease of using the platform tools will determine how much can get done.


    You have inspired me to think more on how to structure a good (likely to be selected) road test application.




    Mark A

  • FPGAs shine when you are talking about a) (massive) parallel computation b) anything where reliable (and fast) timing is critical. Think of oscilloscopes, digital video cameras, high-speed bus systems. a MCU only has limited computational bandwidth, and it cannot guarantee stable timing (apart from interrupts, but using them reduces the available computation bandwidth). FPGAs can handle many things in parallel, and sometimes you need just that.

    As already mentioned, PSoC falls somewhere in the middle. They don't have as much resources as a FPGA (they are more like a CPLD), but with their programmable hardware they can handle timing-critical functions directly in hardware. This leaves the MCU core free to either go to sleep (and save power) or to take care of the more complex and not-timing-critical stuff.

  • I did, maybe, step over the 'a roadtest isn't a design challenge' line there a little, so you're probably right. But there are going to be a lot of people pitching for the 'board as an educational tool' approach, so this is a way to differentiate yourself from that and help TerASIC who will want a balance of the different kinds of roadtest that you might do with it. What you've already proposed is probably enough and I'm just getting enthusiastic and egging the cake a bit.

  • Out of curiousity, how did you do your design for the PSoC (I'm not familiar with the PSoC parts or the Cypress design tools)? Did you synthesise it from a schematic, use a HDL [hardware discription language] like VHDL or Verilog, or was it something else (like, maybe, dragging and dropping circuit blocks)? Just wondering what you're going to have to do to get it into the FPGA.

  • Hi Hendrik,


    I agree.

    Pure FPGA technology provides a developer to work with intricate circuits to handle a wide range of conditions.

    You mentioned a few, but the device itself can be used for a wide range of applications.


    I also agree that the PSOC is a hybrid device.  It provides the user with a limit set of programmable Analog and Digital devices for bridging normal MCU applications with a level of custom circuit implementation capability.

    There are obvious limitations with the PSOC product, but it represents a very useful tool.


    The NEO device introduces a lot of flexibility in a single package.

    I am very interested to see if it can be adequately exploited in the maker arena.

    In some ways it has a tremendous potential.

    On the other hand, the skills and tools may be lacking to fully use the device at this level.


    I hope that the road testers can better define where and who can or should consider this type of product.