Table of contents

RoadTest: Summer of FPGAs -- OrangeCrab Dev Bd

Author: skruglewicz

Creation date: 30 Jul 2021

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: Lattice MachXO3 FPGA Starter kit , XiLink Ultra96

What were the biggest problems encountered?: One of my biggest problems was to get the Toolchains installed and working. It took me 3 tries to get working toolchains up and running to do a simple Blinky example. This has nothing to do with a well built board, but my reviews of MCUs always contained a "Getting Started" page as a springboard to using the software IDE for the evaluation board. It would be nice if this sort of thing was available for beginners of FPGAs. I know that it is open source and that the designer Greg Davill, is a one man shop. The OrangeCrab is priced right for us Hobbyist Makers. Keep up the good work Greg.:>

Detailed Review:

This review will evaluate the embedded software development capabilities of the Orange Crab, an FPGA based Development Board. I will be focusing on the open hardware toolchains available and will conduct experiments using them. I will be exploring the "Hardware Design Language" (HDL) and attempt to bridge the gap I have between it and High Level languages like C and Python, If that is possible.

I will not be touching on the History of or what a FPGA is. There are plenty of resources here on element14 and on the Web on this topic. I have also included some of my favorite references at the end of this review.

Up until now, I have been experimenting and performing reviews on MCU based Dev Boards, using IDE's and SDK's specific to the kit being used. I will attempt to do the same when reviewing this board. I am interested in the "Parallel" aspects of FPGA's  as opposed to "Sequential" properties of MCU based programming I have done Assembler programming, but that was a long..long..long time ago on an 8 bit Z80 Microprocessor. I am a Software engineer by trade and I'm intrigued by the concepts of experimenting with Software on a Chip (SoC) and experimenting with the implantation of proven hardware subsystems that have been etched in silicone. I'm eager to explore the "FP" in the acronym FPGA. The concept, of logic that had been etched permanently in silicone, but now to be able to "Field Program" it over and over again is mind blowing.

In addition to the "Toolchains" available for the OrangeCrab, I will also be checking out how to get started programming the board. I will be evaluating how a novice Hobbyist like myself can experiment with developing solutions without much pain. I will attempt to lay out a "Roadmap for Beginners" of FPGA programming, while I learn it myself.

I will  be evaluating the use and helpfulness of customer support on the Lattice ECP5 FPGA chip, Orange Crab board itself and the Software Development Toolchains available. I will also be discovering and evaluating the available User Forums that hopefully will aid me in my experiments.

Background

• The Orange Crab is designed and prototyped by Greg Davill,  the Feather-compatible OrangeCrab is built around a Lattice Semi ECP5 FPGA, and can have up to 8Gbit of DDR3 memory on board. it is is not only designed by him, but also hand placed and assembled.
• The OrangeCrab, is Open Source Hardware and bears the OSHW badge with pride. It has been created using KiCad, an open source EDA suite.  OSHW is defined on the Open Source Hardware Association site as:
  • "Open Source Hardware (OSHW) is a term for tangible artifacts — machines, devices, or other physical things — whose design has been released to the public in such a way that anyone can make, modify, distribute, and use those things. This definition is intended to help provide guidelines for the development and evaluation of licenses for Open Source Hardware."
• Greg's Hardware Definition can be found on his Git Hub Repository.
• It is fully compatible with the open source FPGA toolchain and flow, with synthesis being handled by Yosys, Place and Route being taken care of by Nextpnr, and Trellis providing the documentation and utilities.
• On doing some preliminary research, prior to receiving delivery of the Orange Crab, I  determine that this was not a widely used board yet, but a fairly new release. For this reason ,I am finding it hard to get an understanding of getting the Software Development tools to experiment with FPGA. There is not as many training video's as Xilink has for it's line of FPGA devices. The price, however is more affordable to the Hobbyist than the Xilink products.

UnBoxing of the Dev Board

My UnBoxing

• I received my Orange Crab in an electrostatic bag, contained in a shipping box from Newark.
• No fancy box or getting started instructions, as I'm use to in my other Roadtest Reviews on MCU development kits.
• My guess is , that they want to keep the cost down.

• n the box. Small things come in big Packages. At least it was protected in Transport to me. Thanks you Element14.	No fancy box to hold the board? Just my Featherlight Orange Crab in it's bag. A nice way to lower the cost.	Class -C cable not included. Again keep the cost down.

   

A Better Unboxing Video

• I found an Unboxing Video on Hackster.io that I thought I'd share with you.
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  • This is worth watching, as it contains visual information on the board and some great links to some helpful Pages.
  • This Video and helpful page links are listed in the references section below.

Is the OrangeCrab Working?

• The OrangeCrab comes out of the box with preinstalled program loaded that will run when you plug it in. It is a simple RedGreenBlue  cycling Blinky example, that flashes the RGB LED on the board
• As the HacksterIO TV Video describes, When you supply power to the USB connector on the board by attaching a USB Class-C cable, the RGB LED starts flashing in 3 colors!

• Here's My Board running Blinky. It's working Hooray!!!!
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• Ok, now that we know the board is working  let's get to experimenting with the Toolchains for this board.

Getting Started

I tried 3 different Open source Toolchains and finally had success with the third one. Here are my 3 Attempts in getting an Open Source Toolchain working for the OrangeCrab development.

PLAN A - Failed

• Since there were no links in the packaged material, I stumbled across the hardware designers web site and found a very helpful Getting Started page.

• This guide should cover everything you need to get the example Verilog project built and loaded up on the OrangeCrab.

• ^Updated08/09/2021 - I tried the link: https://gregdavill.github.io/OrangeCrab/r0.2/docs/getting-started/
• And I received a 404 page not found error? It was there a few days ago? what DO I do now? I was right in the middle installing open tools and the examples?
• PROBLEM With PLAN A
• ^{Updated I noticed that this was back online as of 08/18/2021}

PLAN B - Failed

• OK now that the web page suddenly disappeared it's on the Plan B which is to follow the Toolchain Setup on GitHub  repo open-tool-forge/summon-fpga-tools

• I've documented the steps I followed from this page in Appendix C. I decided to run the script on my Ubuntu development box to make the tools and then run the examples.

• Problem With PLAN B!!
• And my workstation keeps hanging up ???? At different places. I tried running it 5 times. I give up for now.
• This is getting frustrating. But I guess I need to be patient, it is Open Source Software.
• Go on the PLAN C and try it on Windows as described in Appendix D

PLAN C -- SUCCESS

• OK, they say the "third time around is a charm"
• I was able to get an Open Source Toolchain installed on my Windows 10 box. On the GroupGets page, I found a link to a GitHub Repository that worked for me.
• I was able to get the tools installed and get a few Blinky programs made and uploaded to the OrangeCrab and they ran perfectly
• The repo is at https://github.com/xobs/ecp5-toolchain. It contains the prebuilt versions of all the tools needed to develop for an ECP3 board.
• It contains almost everything you'll need to develop on Formu"? whatever that means.
• The following are all built and ready to run: yosys, nextpnr-ecp5, dfu-util,  python3, riscv-gcc, wishbone-tool
• I've documented the installation process I did to get both the tools onto my Windows10 box in Appendix D below. So if your interested then go to the Appendix and load them up, otherwise if you already have them go on to my next section.

• Next I'll experiment with some Toolchains...

Toolchains

Open Source FPGA Toolchains

ECP5 Toolchain

It contains the following tools:

1. yosys -- for Synthesis
2. nextpnr-exp5 -- place-and-route
3. dfu-util -- used with the OrangeCrab dfu bootloader to Upload bitstream to the FPGA
4. python3 -- which I already have, but is used for the nextpnr-ecp5 program and to build  litex projects. Note to Self: I would like to experiment with litex.
5. riscv-gcc -- Compile code for the Risc-V CPUs, such as the Risc-V softcore CPU loaded by the bootloader on the OrangeCrab.
6. wishbone-tool -- Access the wishbone debug bus over USB or SPI.  Note to Self: I would like to experiment with this.

• The open source toolchain is quick to install and fully cross platform.
  • These tools can be installed by following the installation guides on each project, or alternatively there are prebuilt versions.
• The windows version also includes the make utility!. NICE....
• It is recommended that you install and use git to manage repositories and check out code, though it is not necessary. I myself, just grabbed the windows .zip file and unziped it and pointed the path to the bin directory.
• If you haven't installed the tools from Appendix D, you should do so now before following the examples coming up next

Install FPGA examples from Greg Davill's GitHub Repository

• Clone the example Repo at https://github.com/gregdavill/OrangeCrab-examples to you local directory
• These examples use the Vexrisc CPU created inside the FPGA by the bootloader
  • It is worth mentioning ,that the he RISCV firmware is copied into the flash memory by the bootloader .
  • The bootloader is started if you depress button 0 while plugging in the board. This puts the OrangeCrab in DFU mode.
  • You then load the RISCV firmware you build using the dfu tool.
  • If the bootloader determines that it has not loaded a new gateware ,
  • then the CPU will simply adjust it's program counter to start executing the newly loaded program.

RISCV Blink examples

There are 2 blink examples under the /riscv directory

• In order to run the examples go to the directory and open the README.md file
• This will give you instructions on how to build and upload the program.
• -

blink

It blinks the LED

The Following text  is taken directly from the README.md file.

this is how to run the example.

------------------------------------------------------------

-------------------------------------------------------------

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button

Reads input from button, toggle through colors on the LED

------------------------------------------------------------------------------

1.      $make clean

2.     Enter the DFU bootloader by holding the button while connecting OrangeCrab to your USB port

3.     $make all

4.     $make dfu

-----------------------------------------------------------------------------

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Verilog Blink Examples

There are 4 blink examples under the /verilog directory

• In order to run the examples go to the directory and open the README.md file
• This will give you instructions on how to build and upload the program.
• I tried all 4 but I'll document what I did for the first example, called blink.
• These are excellent examples for using the toolchain and using HDL to program the FPGA using HDL.
• This is a different concept in that,  this logic will run directly on the FPGA without any CPU softcore.
• If you view the README.md file, a singular Verilog file "blink.v" describes a module that increments a 27 bit counter.
• To run this demo
  • cd to the blink directory
  • Enter the DFU bootloader by holding the button while connecting OrangeCrab to your USB port
  • Then build and upload the code by simply typing  the following command:

          $ make dfu

• The make build script will produce the bitstream from the HDL. It makes uses of the open source tools `yosys`, `nextpnr`, `ecppack`, and `dfu-util` to go from hardware description to bitstream to running on the FPGA.
• I had a minor problem running the example and was getting the following error
  • make: *** [Makefile:38: blink.bit] Error 1
• This reveled that there was an unsupported argument on the ecppack command in the makefile! My version of ecppack that I have must be an older version then the exampls repo.

ecppack --compress --freq 38.8 --input blink_out.config --bit blink.bit

Error: unrecognised option '--compress'

• Removing the "--compress" argument in the makefile resolved this issue and I was able continue with the example. I did this in all the Verilog make files for all the other examples and was able to run them all. I'll be sure to figure out which version of ecppack supports the --compress arg, but for now I'll continue on with finishing up this review.

• My first Verilog program running on my OrangeCrab !!!

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Summary & Conclusions

Some Questions?

• I posed some question to myself while learning about FPGA Toolchains. Some are answered and some are still unanswered.
  • Can you place this board on a Breadboard?
    • ANS: seems so with headers. I'd be interested in what you folks feel. My soldering skills are minimal!
    • If so, Some projects ?
  • Can you use any Toolchain for the Orange Crab?
    • ANS: Depends
    • Do you have to use Lattice tools?
      • ANS: NO
    • Can you use Verilog?
      • ANS: YES
    • Can you use Xilinx VivaDdo?
      • Vivado has simulation tools, so you can play around with those while you wait for your hardware! Does Lattice have a simulator?
  • How easy is it to implement a simple Blinky Experiment?
    • ANS: YES .... I came to answer this myself
  • Can you run toolchains on windows 10?
    • ANS: YES
    • Lattice Diamond will install on Windows10
    • The open source tools used in this review do
    • Ran Greg's examples
  • Can you run the Greg Davill suggested open tools and example on Windows10
    • ANS: NO
      • Tried to but, did not succeed

Summary

• After I was selected as a Road tester and Prior to getting the OrangeCrab, I spent the time scoring the internet on anything I could find to the OrangeCrab, FPGA, and toolchains.
  • I started noting those pages I spent time on in the References section of this review.
  • I created an account on the Lattice Website.
    • I utilized the Lattice Customer support Portal and getting a quick response to my inquires. Very useful site.
  • I went to the GroupGets OrangeCrab site and learnt about there services. This is one of my go to pages to learn about the board.
  • I read the blogs on the OrangeCrab on the Hackster.io site.
  • I started compiling a "Glossary of Terms" that I defined in Appendix A.
  • I tried to install Greg Davill "Getting Started" tools on Windows10. Did not succeed?
  • Next i tried to install on Ubuntu (Refer to Appendix C), without success.
• Then when I received the board,
  • I took some UnBoxing Pics and referred my readers to an excellent Hakster.io TV video on there unboxing of the board.
  • I was surprised to see the bare-bones packaging(no getting started?),
    • but I did stumble onto an Open Source toolchain suite that I was able to install on my windows box.
    • This installed like a charm on my windows 10 installation, but it is a couple of years old. It seems to be pretty stable and the tools are prebuilt which means that they must be out-of-date, but I have not run into any major issues yet.
  • I then, cloned the Greg Davill examples on my box and began running the examples. That went really well, and I got to get comfortable with toolchain and programming for the FPGA
• I have just scratched the surface with my experimentations using this board and will continue using it to experiment with software development on an FPGA.
• I have included a wish list of "Possible Future Experiments" that I am interested in trying out below.

Conclusion

• This review was a challenge for me, since I had no FPGA software development knowledge prior to this review.
• But I do have a degree in computer science, did some Assembler, and have been a programmer for many years.
• From what I've been reading and pricing other FPGA based development boards, the OrangeCrab is an excellent entry level tool for experimenting with the technology for low budget makers, like myself.
• That said, when it came down to scoring using the roadtest template list, I had a hard time evaluating objectively as a student of FPGA software development on a entirely foreign piece of tech to me.
• I would like to touch upon my reasons for scoring like I did.

• Scoring Revisited

  • Product Performed to Expectations: 10

  • I gave this a 10,  because this product stood up to all my preliminary research that I conducted prior to getting the board. Everything I read about it came true. I am still finding things to do with this tech. Good job in your Design Greg Davill!

  • Specifications were sufficient to design with: 5

  • I gave this n 5, because where there are plenty of hardware diagrams on the git repo, there is a lack of software development flows. I had trouble understanding at first the concepts of the bootloader and the memory components for one.

  • Demo Software was of good quality: 6

  • I gave this a 6,  The examples that Greg Davill has for the board are excellent and self documenting. They helped tremendously in getting to understand software development. But, I was disappointed when your web site (https://gregdavill.github.io/OrangeCrab/r0.2/docs/getting-started/ ) disappeared. I was using it as a Getting started springboard and when I got the board in my hands, it disappeared? It seemed like a good start for beginners. Maybe if you see this review you can get it back up soon?
  • ^{Updated I noticed that this was back online as of 08/18/2021}

  • Product was easy to use: 8

  • I gave this an 8, because so far, the examples are working great. The bootloader works great to upload my logic.

  • Support materials were available: 5

• I gave this a 5, because of the lack of  support and could not find any online support or forums to help me get my toolchains installed. I had to really search the internet for answers . I didn't experience this when evaluating MCU boards from NXP, Arduino and others. This area could use some improvement. It seems like your a one-man shop, and this is understandable

• The price to performance ratio was good: 10

• I gave this a 10, I'm a retired hobbyist and I'm on a budget. I would love to experiment with XiLink products, but cannot justify the price. Also the fact that the price could be less due to GroupGet buying campaigns make it more attractive to folks like me. and of course the Open Source software development support and the OSHW certification make it very attractive

Possible Future Experiments

Lattice Toolchains

• Create an account on the Lattice Website.
  • Utilize the Lattice  Customer support Portal
• Install Lattice Diamond IDE on Windows10 and/or Ubuntu
  • Run through the Training Videos.
  • Use the Verilog examples used by the open source toolchain to experiment with using the Lattice Diamond IDE ECP5 support.

Linux on the OrangeCrab

• An Example of running Linux-On-Litex on the OrangeCrab.
• Other HDL examples with Lattice Diamond IDE and/or Open Source Toolchain.

MicroPython + CircuitPython

• This is still a work in progress!
• Plug the board in and start blinking LEDs straight away with no external tools required.

RISCV firmware

• Install the RISCV GCC compiler and start programming the board, code is executed on the SoC created by the bootloader.
• Excited to do IoT on a RISC Architecture.

FPGA gateware

• Update the FPGA gateware using Verilog or other Higher level language: nMigen, Litex, Chisel, etc.

JTAG Debugger

• Use the board features of a standard 0.05" JTAG connector. The ECP5 can be reprogrammed directly over JTAG or using a SPI bypass mode, and the onboard FLASH can be read/written over JTAG.

Appendices

Appendix A -- Glossary of Terms

Here are some helpful acronyms defined, that I've seen in researching FPGA's

• FPGA: A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence “field-programmable“.

• gateway--  the logic that is used to execute a function over the CPU softcore on the FPGA.

• PWM: (Pulse-width modulation), or pulse-duration modulation (PDM), is a method of reducing the average power delivered by an electrical signal, by effectively chopping it up into discrete parts. The average value of voltage (and current) fed to the load is controlled by turning the switch between supply and load on and off at a fast rate.

• HDL: (Hardware Description Language). The two most popular HDLs are Verilog and VHDL

• Verilog: Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits

• VHDL: VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

• Bitstream: The file that configures the FPGA (has a .bit extension). The bitstream gets loaded into an FPGA when ready for execution. Obtained after place and route, final result of the place and route phase.

• Synthesis: Process of creating a netlist from a circuit description described using HDLs (Hardware Description Language), HLLs (High Level Language), GUI (Graphical User Interfaces).

• FPGA chip: Unlike microcontrollers where you only have control over the software, with FPGA you have control over the hardware as well. There is no processor to run software on, at least until you design one! You can configure an FPGA to be something as simple as an and gate, or something as complex as a multi-core processor. To create your design,
  • you write some HDL (Hardware Description Language).
  • You then synthesize your HDL into a bit file which you can use to configure the FPGA.
  • SoC (System on Chip) is used to distinguish between Zynq and non-Zynq parts (Zynq is an SoC which includes a processor).

• FPGA fabric:  The internal structure of an FPGA.
  • The various devices that the FPGA contains,
  • the type of interconnect,
  • the add-on features and so on.
  • For example, a typical FPGA from Xilinx or Altera has a combinatorial logic block(CLB) which typically consists of a lookup table (LUT) which can be configured for 2 to 7 inputs, an adder and a D flip-flop. This forms the logic element in the FPGA. The FPGA also contains other blocks like phase locked loops (PLL), I/O buffers, block memory (BRAM), Digital Signal Processing (DSP) blocks and in some cases macro blocks which function as a PCIe controller, Gigabit Ethernet controller, Serializer/Deserializer (SERDES) and off late even large blocks like video codecs (h.264 and h.265 in Zynq Ultrascale+). All of these blocks are programmable and configurable via RTL but need not be designed as we’d do in the ASIC flow. (Except for the FPGA manufacturer of course).

• LUT:  A LUT, or lookup table is a fast way to realize a complex function in digital logic. The address is the function input, and the value at that address is the function output. The advantage is that computing the function only takes a single memory lookup regardless of the complexity of the function, so it is very fast.

• Hard-core vs. soft-core: A hard-core processor is a processor that’s actually physically implemented as a structure in the silicon. Basically, you can add a soft-core processor to a FPGA-based system after it’s already designed. However, adding a hard-core processor requires either a different FPGA, or an additional chip on the board.

• FPGA firmware: Though the code deployed on the FPGA is sometimes referred to as its firmware, this is a slight misconception. Firmware is indeed embedded and dedicated code, but the code is executed. FPGA code is written in a description language, then is interpreted, synthesized, and ultimately produces hardware. So, I see it fit to refer to the FPGA, when it is configured, as hardware, and to the code itself as a description language.

• IP core: An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array ( FPGA ) or application-specific integrated circuit ( ASIC ) for a product. They are reusable/portable between many different designs.

• FPGA clock: All logic executing within the fabric of an FPGA must be based upon one or more timeframe references more commonly called “clocks.” On the FPGA module, clocks are used to synchronize read/write operations, synchronize data transmission and capture, control the timing of data processing, and prepare data for storage. For example, it may take some multiple of 8 clock cycles to process and prepare a single 8-bit byte of data for storage in a memory device.

• Synchronous: Typically describing a system that operates on a single clock.

• FPGA architecture: FPGA architecture is how the chip is designed/structured, rather than the chip itself. The precise architecture of an FPGA varies from manufacturer to manufacturer.
  • The FPGA Architecture consists of three major components
  • Programmable logic blocks: Logic blocks can be formed from thousands of transistors to millions of transistors. They implement the logic functions required by the design and consist of logic components such as transistor pairs, look-up tables (LUTs), and Carry and Control Logic (flip flops and multiplexers).
  • Programmable I/O blocks: They connect logic blocks with external components via interfacing pins.

• Programmable interconnect resources: They are electrically programmable interconnections (pre-laid vertically and horizontally) that provide the routing path for the programmable logic blocks. Routing paths contain wire segments of varying lengths which can be interconnected via electrically programmable switches. The FPGA density depends of the number of segments in use for routing paths.

Appendix B -- Lattice Diamond IDE

You will need a free license file otherwise you receive this error when trying to run the IDE.

To get a license file follow the install guide for windows by downloading the install guide at  Lattice Diamond 3.12 installation guide for Windows .

Appendix C -- Installing the Open-source FPGA tools on Ubuntu

• Go to the GitHub repo for the Summon-FPGA-Tools.
• I did not install the latest nightly builds? Should I have?
• First I installed the Dependencies (I skipped over this the first time through and got an error because the make utility was missing)
  • sudo apt-get install git mercurial build-essential bison clang cmake \
  flex gawk graphviz xdot libboost-all-dev \
  libeigen3-dev libffi-dev libftdi-dev libgmp3-dev \
  libmpfr-dev libncurses5-dev libmpc-dev \
  libreadline-dev zlib1g-dev pkg-config python \
  python3 python3-dev tcl-dev autoconf gperf \
  qtbase5-dev libqt5opengl5-dev
• Then I cloned the repo
  • git clone https://github.com/esden/summon-fpga-tools.git
• I then compiled the open source by running the shell script as follows

  • cd summon-fpga-tools

  • ./summon-fpga-tools.sh

• And my workstation hung?????
• ERROR:

At different places Go on the PLAN C and try it on Windows as described in Appendix D

• TODO if I ever get it built

• Set the path to point at the tools bin directory
  • export PATH=~/sft/bin:$PATH
• GO BACK to STEP 1 in the Setup Instructions  and test that the tools were installed properly by running
  • $ yosys -V
  • $ nextpnr -ecp5 -V

• On linux based systems you may also need to add a udev rule to enable user access to the usb device, once added you’ll need to un-plug and reconnect the OrangeCrab for it to take effect

$ cat /etc/udev/rules.d/99-orangecrab.rules

ATTRS{idVendor}=="1209", ATTRS{idProduct}=="5af0", MODE="0666", GROUP="plugdev", TAG+="uaccess"

• NEXT..
  • Run through Step 2: Verilog example

Appendix D -- Getting the Open Source ECP5 FPGA Toolchain on Windows10

1. Go to the GitHub repo at https://github.com/xobs/ecp5-toolchain
2. Download the latest release for your platform.
3. Download the ZIP file
4. Unzip the file to your disk.
5. Set path to Bin directory
   • Windows cmd.exe: PATH=[path-to-bin];%PATH%
   • PATH = ..\ecp5-toolchain-windows-v1.6.9\bin;%PATH%
6. Test - To confirm installation, run a command such as nextpnr-ecp5 or yosys.

Additionally, the macOS and Windows versions include make.