Summer of FPGAs -- Lattice Certus-NX Versa Eval Bd - Review

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RoadTest: Summer of FPGAs -- Lattice Certus-NX Versa Eval Bd

Author: pandoramc

Creation date: 16 Nov 2021

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: There is not a product that I can compare at the moment

What were the biggest problems encountered?: The memory IP implementations. Software Freezing with 'No' option selected to update the netlist when is open

Detailed Review:

Introduction

The following work is based on the book The Elements of Computing Systems, second edition: Building a Modern Computer from First Principles of Noam Nisan and Shimon Schocken.

In order to develop an small implementation and hybrid design for the HACK Computer System, the provided tools in the site https://www.nand2tetris.org/ by the authors will be used to validate and get reference images for the work. In addition, the Lattice Radiant software and IP catalog is used to made the architecture. I hope you find this road test useful and special thanks to rscasny and sponsors for this oportunity.

The first steps

Let’s test the board. The kit contains the evaluation board, a 12V AC/DC adapter, a USB-A to Mini-B for programming and the Quick Start Guide. As the board is used in a surface and there are alot of components in the bottom side, I added four 5 mm spacers to hangle the board and minimize the damage risk.

Fig 1. Kit unboxing and additional setup

The board is preset for its use with Lattice Radiant Software with minimal or without additional setup. If the board is connected to the PC by the Mini-B a small LED between the connector and the FTDI IC turn on and you will notice that a device is not connected physically in the PC. You should connect the 12V Power supply in J35 to energize the board and detect it. This process is described in the quick start guide. Now on Radiant Software a counter with BCD decoder is implemented. The process involves the Lattice IP Catalog and own code.

Why IP catalog?

Some entities are hard or soft implemented in the devices. In order to improve the Logic Design workflow, there are two approaches: Implementation and Interface. Implementation consists in the full logic design of a device, while Interface use well-defined code by 3rd party designer and only an instantiation is needed. The counter is available in most of IP Catalogs. For the Lattice IP Counter we have the follow interface,

Fig 2. Counter Lattice IP

For this demo, the counter is configured as Up/Down counter from 0 to 10 because the BCD decoder will work with 10 symbols. For the BCD, the description is needed because there is not a soft implementation about it. In addition, We need consider that I/O are negative logic board implementation.You can use the Source Template for quick implementation about the HDL skeleton.

-- Library and Use statements for IEEE packages
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BCD_Decoder is
        port(
                A      : IN    STD_LOGIC_VECTOR(3 DOWNTO 0);
                Y      : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0)
        );
end BCD_Decoder;
ARCHITECTURE behavior OF BCD_Decoder IS
        signal aux: std_logic_vector(7 downto 0);
BEGIN
     WITH A SELECT aux <=
           "11111100" WHEN "0000",
           "01100000" WHEN "0001",
           "11011010" WHEN "0010",
           "11110010" WHEN "0011",
           "01100110" WHEN "0100",
           "10110110" WHEN "0101",
           "10111110" WHEN "0110",
           "11100000" WHEN "0111",
           "11111110" WHEN "1000",
           "11110110" WHEN "1001",
           "00000010" WHEN OTHERS;
     Y <= NOT aux;
END behavior;

The clock is relatively fast for visual results, consequently a clock divider is added.  If we Synthetize design, an RTL diagram is generated. It can be observed with the Netlist Analyzer tool. In addition, the Split Tab option in Window Menu allow the navigation between RTL and Description. A double click on the entity will highlight the section that implements it. Furthermore, the secondary click Menu has the Dissolve Instances to visualize the implementation. An interesting feature is green colored clock lines.

Fig 3. RTL View for the Counter BCD Demo.

Once the RTL is valid, the Device Constraint Editor allows a definition of external connection of the FPGA. If you are not sure about the power scheme for I/O, the User guide shows this information in two sections. One for Power scheme of I/O banks and one for Hardware implementations as LEDs and Switches.

Fig 4. Constraint Device.

For programming, we need Export files before open Programmer interface. Only the correct programming port must be selected and after the programming, the magic occurs.

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Demo Video for the BCD Counter

HACK Computer System

There are some limitations about the original HACK Computer System for this board. There is not a direct Video output and keyboard input, consequently, the memory map is reasigned to the Switches, LEDS, and 7 Segment Display. This will be called Peripheral memory as a microcontroller.

At the core of the implemented HACK CPU, the Arithmetic Logic Unit (ALU) can be found. For the first design step, the ALU is implemented. we can follow the next table, where the base supported instructions by the processor can be implemented.

Table I. HACK CPU Instruction Set Architecture

The control bits are Z, N and A/L for Zero output, Negate output and Arithmetic/Logic respectively.

As the initial design, the preset input component for X and Y input vector is proposed. From the truth table, the following circuit can be inferred.

Fig 5. Input preconditioner

The preset allows a pre-condition of the input for the arithmetic and logic operations. According to DeMorgan laws, this preset achieve logic and arithmetic operations only with some multiplexers, an Adder, and some primitive gates. We can implement the following VHDL code to infer the circuit above.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PRE_CONDITION IS PORT(
     A  : IN   STD_LOGIC_VECTOR(15 DOWNTO 0);
     C  : IN   STD_LOGIC_VECTOR(1 DOWNTO 0);
     Y  : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END ENTITY PRE_CONDITION;
ARCHITECTURE ADJUST OF PRE_CONDITION IS
     SIGNAL zero_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
     zero_A    <=     (OTHERS => '0')    WHEN C(1) = '1' ELSE
          A;
     Y         <=     NOT zero_A   WHEN C(0) = '1' ELSE
          zero_A;
END ARCHITECTURE ADJUST;

After the command Synthesize Design, it is possible view the RTL diagram with the command Netlist Analizer. It is important to visualize in paper the target circuit to optimize and reduce the design synthesizing divergence. An example is the following.

(a)

(b)

Fig 6. Synthesis differences about logic perspective

The figures above show a minimal divergence according to the conditional perspective. When negative logic perspective is considered, a not gate is added in the multiplexer control input (b), while positive logic is not (a). The code is the same, but the next lines, with negative logic, are implemented for the figure (b)

zero_A <=     A      WHEN C(1) = '0' ELSE
     (OTHERS => '0');
Y            <=     zero_A WHEN C(0) = '0' ELSE
     NOT zero_A;

The memory map

The first implementation about the HACK Computer System need replace the keyboard and monitor for smaller devices. This means that the HACK Computer System now is a microcontroller . At the moment, the memory map has 3 pheripherals: Switches, LEDs and 7 Segment display

Table II.Peripheral Memory Map

According to HACK design, the RAM Memory has 16K, after that the peripherals are implemented, consecuently, the Peripheral address offset is 16384. This should be considered when the computer system is implemented.

(a)

(b)

Fig 7. HACK implementations. (a) own implementation (b) courseware proposed implementation. Source: https://www.nand2tetris.org/course

The test

For architecture testing, a software Hex-BCD is implemented in the following way.

1. The BCD Lookup table codes are loaded in the RAM memory
2. The Switches peripheral is read and anded to remove the second nibble.
3. The look up table address is readed and add the number to show the BCD code, this acts like a pointer.
4. The look up table value is negated and writed in the 7 segments display to accomplish the physical implementation.

The algorith described is reached with the following code HACK Assemble code.

//Load Look Up table for each BCD code
@63
D=A
@DISP0
M=D
@6
D=A
@DISP1
M=D
@91
D=A
@DISP2
M=D
@79
D=A
@DISP3
M=D
@102
D=A
@DISP4
M=D
@109
D=A
@DISP5
M=D
@125
D=A
@DISP6
M=D
@7
D=A
@DISP7
M=D
@127
D=A
@DISP8
M=D
@111
D=A
@DISP9
M=D
@119
D=A
@DISPA
M=D
@124
D=A
@DISPB
M=D
@57
D=A
@DISPC
M=D
@94
D=A
@DISPD
M=D
@121
D=A
@DISPE
M=D
@113
D=A
@DISPF
M=D
// Read the DISP Look up table base address
@DISP0
D=A
@BCD_BASE
M=D
// Looping for continuous work
(LOOP)
    // Read the peripheral switches value
    @16384
    D=M
    // Show the peripheral switches value in peripheral LEDs
    @16385
    M=D
    // Take the 4 least significant bits
    @15
    D=D&A
    //point to the look up input position
    @BCD_BASE
    A=M+D
    // Get the value in the memory address
    D=M
    // Show the not operation in the peripheral 7 Segments
    @16386
    M=!D
// Loop to continuous process
@LOOP
0;JMP

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In addition, you can validate most of your designs with the ModelSim Lattice Simulator. Remember, it is a simulator and all must be defined for thaat purpose. In the physical implementation chain, the software warn you about initialization omisions because and unknow technology defined in the device constraint editor or sinthesizing process.

Fig 8. ModelSim section for the algorithm validation

Issues

The software did not allow configure DIP_SW1, DIP_SW3 and DIP_SW4 as LVCMOS15 as shown in the User Guide. According the board documentation the J16 configures the VCCIO for the banks 3 and 4 to 1.5V, default, or 1.2V. Despite this configuration, in the Certus-NX Family Preliminary Data sheet on page 56, the Bank 3 and 4, where the Switches are, does not support the LVCMOS15 configuration. In addition, the software shown LVCMOS33(LVCMOS18H) at the end of implementation flow. This brings a configuration confusion about this ports. I did not found at this moment a Full BSP constraint file, consequently, some terminals should de declared according manuals.

Fig 9. Device Constraint Software Correction

The memory IP had a problem in the simulation and the implementation tasks. When I try simulate a EBR RAM and EBR ROM in ModelSim the simulator shows an error and I cannot simulate the design behavior. Finally, the implementation process removes the instances and the design is not funtional. There is not a quick reference to solve it. Furthermore, the IP generation is only available in Verilog but it is possible to use in VHDL with the Copy VHDL Instantiation available in the secondary click menu for the IP generated. rare times the EBR RAM works but I am not sure the reason.

Fig 10. ModelSim EBR Memory block IPs Instatiation Failure.

At programming time, the first time has no problems, but for a other programming I need push the PROGRAM button and wait about 2 seconds. I do not know if this is normal behavior, It is a kind of cold programming. Some times, this not work properly, the system freezes, and I need unplug power supply to restart the board