RoadTest: Summer of FPGAs -- OrangeCrab Dev Bd
Evaluation Type: Development Boards & Tools
Did you receive all parts the manufacturer stated would be included in the package?: True
What other parts do you consider comparable to this product?: The 20LE development board from SEEED is similar in form factor and also uses the same Yosys open source FPGA tool chain.
What were the biggest problems encountered?: I had success compiling basic designs. However I was not successful when I tried to compile a more substantial design.
Before starting my review I would like to thank Randall for allowing the extension to produce this RoadTest review as I was having some medical difficulties during much of the original time frame.
I would also like to extend my appreciation to GroupGets and the creator of the board for their patience.
The OrangeCrab is an FPGA development board that was designed by Greg Davill and available through GroupGets. It's a tiny board made to the feather standard and has dimensions of 0.9" x 2.0".
Its key component is the Lattice ECP5-25F FPGA, which is further complemented by 128MB of DDR and a 128Mbit QSPI FLASH memory. The board is designed for open source FPGA development using the Yosys toolchain. Additionally the product also serves as a platform to test and develop for the RISCV soft processor.
Although I was excited to experiment with the OrangeCrab board I was a little apprehensive about the open source design methodology. To prepare for the RoadTest I had bookmarked a number of links to help me get started with the board.
Unfortunately the links for these open source resources were all broken by the time I received the board.
Luckily I was able to benefit from the ground work carried out by fellow Road Tester Stephen Kruglewicz. Steve was a real trail blazer here. He posted a very detailed Road Test before I cracked the box open. Okay, I had managed to peak inside and snap a few glamour shots but not much more than that.
From Steve's review I learned where to download the tool chain and design examples.
His guide for downloading and installing the tool chain can be found here:
His guide for getting started with the pre-built examples can be found here:
Running the Design Examples
The RISCV examples essentially allow you to compile C code and deploy it to the OrangeCrab where it is run on a soft RISC processor.
In the Verilog examples the HDL code is compiled and uploaded to the OrangeCrab to be executed as RTL. In this review we'll focus on this latter type of example.
The most basic example included in the Verilog designs is the blink example.
To 'run' this example do the following:
In Windows Command Prompt set path to the location of the tool chain.
In my case this was:
PATH = c:\ecp5-toolchain-windows-v1.6.9\bin;%PATH%
Navigate to the ..\OrangeCrab-examples-main\verilog\blink folder
To compile the design type: make <ENTER>
To upload the compiled code do the following:
While pressing the BTN0 button connect the USB cable to the PC.
Release the button and type: make dfu
When the upload is completed the LED will flash red, green and yellow.
After running the example designs I was pretty confident that the open source Yosys compiler was capable of handling basic HDL constructs but what about something more exotic like a PLL?
For this experiment I momentarily stepped outside of the open source work flow to use the Clarity module within the Lattice Diamond software to generate a Verilog file for a PLL that produces a 24MHz clock from the 48MHz input clock.
And then it was back to the open source tool chain.....
I had discovered that the make file for the pwm_rainbow example was useful in that it could handle hierarchical designs; i.e. designs with multiple Verilog files.
I copied over the pwm_rainbow make file and renamed it to blink_pll.
I edited this file by making the following changes:
PROJ=pwm_rainbow was changed to: PROJ=blink_pll
ecppack --compress --freq 38.8 --input $< --bit $@ was changed to: ecppack --freq 38.8 --input $< --bit $@
Upon compiling I was confronted with the following error:
ERROR: Module `\VLO' referenced in module `\pll_48_25' in cell `\scuba_vlo_inst' is not part of the design.
After some trial and error I made the following changes to the Verilog file:
I replaced the following 2 lines:
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
assign scuba_vhi = 1'b1;
assign scuba_vlo = 1'b0;
This time the compile went off with no errors and when the firmware was configured the LEDs flashed at a lower rate as expected.
I was quite pleased to see that the open source tool chain handled a PLL based design so well.
In the last year or so I've been very interested in adding video functionality to my FPGA designs. Of course I recognize that the world has moved to HDMI for some time now, but my experiments are focused on VGA.
FPGAs are well suited to VGA since the red, green and blue component video signals can be generated with ladder DACs. In this method the 1's and 0's produced by the FPGA I/O pins drive resistors in order to create the desired colors.
I designed a simple PCB for these video projects. The PCB is an adapter board that allows an Arduino to interface with the OrangeCrab board. The PCB also includes a VGA adapter for video output.
As far as progress is concerned, the underlying Verilog for the video generation is nearly done. However, there are a number of compiler errors to resolve, and while it would be nice to work through bugs and present a screenshot of a working project, this RoadTest is already long overdue.
This experience with OrangeCrab was my first foray into the world of open source FPGA development, and while there were some hurdles along the way, I had a lot of fun with the board.
In terms of recommendations, the OrangeCrab board is best suited for those who are patient and receptive to an open source workflow.
I for one, plan to continue working with the OrangeCrab board to develop my VGA based video generation project.