Terasic P0082 DE0-Nano FPGA Development Kit - Review

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RoadTest: Terasic P0082 DE0-Nano FPGA Development Kit

Author: davide.bellizia

Creation date:

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?:

What were the biggest problems encountered?:

Detailed Review:

Introduction
I am into FPGA world since the MD, and during the PhD i've intensively used several FPGAs from different vendors and families. This board is very helpful for the expert as well as for a newbie, since it has everything you need to start. I recommend newbie to buy this one, it worths every buck!

Unboxing

The DE0-NANO FPGA board is equipped with a mini-USB type B cable, which allows to power the board and provides the cable connection for uploading the firmware to the FPGA. On the item list, it is reported that the box contains a CD, with the Altera’s developing environment and some extras about the DE0-NANO FPGA development board, but, actually, there are no CDs inside the box. It was not a big problem for me, since I’m not a newbie about Altera’s FPGA, and everything I needed was already on my computer.

 

The board has a very compact size (7.5cmx5cm), and it comes with a nice plexiglass protection. Only connectors are left out of the protection of plexiglass’ perimeter, in order to have easy access to main functionalities of the board. For any problems, or in the case of a very geeky user (like me), it is possible to remove the protection.

   

The board

The board has several nice features, which make it a very precious development board for a newbie. The first thing that I could notice is the presence of an USB Blaster circuitry on board, making the upload of the firmware supereasy. The DE0-NANO FPGA dev. Board has an on-board digital accelerometer, a 32MB of SRAM, 8-channels A/D converter, 2kbit EEPROM, 2 pushbuttons+4 DIP switches and 8 green leds. The board is featured also by 2 40-pins GPIO header (plus an extra one which faces the bottom side of the board), providing connections with the FPGA and with the multichannel A/D converter. Least but not last, the FPGA in the TerasIC DE0-NANO FPGA development board comes with the Altera Cyclone-IV EP4CE22F17C6N. The FPGA, manufactured with a 65nm process, is a very helpful developing system, that allows designers to implement mid-sized project, since it has 22k LEs. As other dev. Boards, the DE0-NANO FPGA board has an on-board EPCS memory, to store the firmware for the Cyclone-IV FPGA.

 

Example of usage

During the Roadtesting I have experimented 3 design. All of them have been developed in Altera Quartus  II13.0 Web Edition. The first one has the aim to play with the digital accelerometer provided on board. The 3-axis accelerometer can forward output data via I2C connection. It is already connected to the FPGA, and the user has to design only the glue logic and the processing circuitry to elaborate the data provided by the sensor. Since I have already some codes ready-to-use in my library, I’ve used a simple I2C ip-core to interface the FPGA with the sensor. At the power-on, a finite state machine sends the configuration settings to the accelerometer. Every 100ms, the FPGA requests a measurement to the sensor, which provides the measurement through I2C. After the receiving of the measurement, the finite state machine forwards the data to the processor, implemented in the FPGA, which adapts the format to the thermometric scale. The converted value of the data received are displayed by the 8 green leds mounted on-board. Since the accelerometer can provide measurements within 3-axes, the user can choose a given axis using the 4 DIP switches before the power one.

 

The other two designs are closely related to my PhD experience (Power Analysis Attack and countermeasures). I tried two different implementation of the PRESENT-80 block cipher using two different logic styles: standard CMOS and WDDL. The WDDL style is a dual-rail pre-charge logic style, and it requires a custom design library for registers and basic combinational gates. Both of them have been tested under a functional points of view. The 50MHz clock provided by the on-board oscillator has been scaled to 10MHz, which is closer to classic lightweight implementation of block cipher for IoT applications. To obtain such scaled clock, the on-chip PLL has been used. The cryptographic core has been embedded with a finite state machine and with a custom UART interface (using an USB-FDTI daughter board connected through one of the 40-pins header), and a custom MATLAB script has been used to communicate with the FPGA. The MATLAB script sends both the 80-bits key and the 64-bits plaintext. Once the receiving is completed, the cryptographic implementation sends back the 64-bit ciphertext using the UART interface. The MATLAB script reads the ciphertext and displaying it on the screen.

Summary

In this RoadTest, the TerasIC DE0-NANO FPGA development board has been tested. Since I am really familiar with Altera’s FPGAs, I had no problem in using it, and I think it is a really good starting point for a newbie. For my needs is perfect for functional testing of cryptographic circuits, since it does not provide any exposed connections for power supply pins/pads of the FPGA’s core (power supply of logics inside the FPGA), thus, it is not possible to use for Power Analysis Attacks and evaluations. Maybe, it can suit very well less invasive analysis (for the board), such as Electro-Magnetic Attacks.

Anonymous
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  • Hi DAB,
    thanks for kind comments! It is the first time and i was a little bit worried about writing the roadtest...

     

    Basically, I have designed a PRESENT-80 block cipher, which is a symmetric encryption primitive. It is widely used in ultralightweight cryptography because it is substantially smaller compared to an AES-128...It is very simple to implement if you don't care about power analysis and something like that, because it is some combinational logics and registers, plus circuitry for controlling multiplexers (FSM can handle the job)...The problem arise when you come to secure it under Power analysis point of view, since it requires a deeper knowledge on what is the behavior of the logic in power consumption domain, and how you can design the whole thing minimizing the information leakage that you can exploit using dynamic and/or static power. The WDDL style is very basic in counteracting power analysis attacks, because it makes use of a dual rail pre charge logic approach to balance the power connsumption, aiming to make it independent from the data processed. In FPGA is a little bit more difficult to implement, and more critical will be its effectiveness (additional and exploitable information leakage due to capacitive mismatch). The CMOS implementation uses 5% of total LCs and 3% of regs, while the WDDL requires almost double of both.
    If you want to know a little bit more about, I have several publications on this topic, you can read them out on IEEE Xplore, LNCS from Springer, etc, or from other sources (try to search me on google scholar or research gate: Davide Bellizia).

    In a regular PAA scenario, you should have the access to manipulate the main VDD pin/s that feeds the power supply voltage to the core of the chip (not the pad ring). It is recommended in order to get the maximal bandwidth  avaible outside the chip, to mount the attack/analaysis. In a real scenario, this requirement often forces you to cut traces on board or something like that. On the DE0 board, you have no access to the real VDD line, but you can only measure the current absorption before regulators, which implies to work with a significantly smoother bandwidth. Using the DE0 board to do this means violating the warranty on the product. As far as I know, excluding SASEBO/SAKURA boards which are designed to work with PAAs, only STM32 Nucleo boards have an accessible jumper to measure the direct absorption of the chip after the regulator.

    Thanks again for your feedback!

     

    Davide

Comment
  • Hi DAB,
    thanks for kind comments! It is the first time and i was a little bit worried about writing the roadtest...

     

    Basically, I have designed a PRESENT-80 block cipher, which is a symmetric encryption primitive. It is widely used in ultralightweight cryptography because it is substantially smaller compared to an AES-128...It is very simple to implement if you don't care about power analysis and something like that, because it is some combinational logics and registers, plus circuitry for controlling multiplexers (FSM can handle the job)...The problem arise when you come to secure it under Power analysis point of view, since it requires a deeper knowledge on what is the behavior of the logic in power consumption domain, and how you can design the whole thing minimizing the information leakage that you can exploit using dynamic and/or static power. The WDDL style is very basic in counteracting power analysis attacks, because it makes use of a dual rail pre charge logic approach to balance the power connsumption, aiming to make it independent from the data processed. In FPGA is a little bit more difficult to implement, and more critical will be its effectiveness (additional and exploitable information leakage due to capacitive mismatch). The CMOS implementation uses 5% of total LCs and 3% of regs, while the WDDL requires almost double of both.
    If you want to know a little bit more about, I have several publications on this topic, you can read them out on IEEE Xplore, LNCS from Springer, etc, or from other sources (try to search me on google scholar or research gate: Davide Bellizia).

    In a regular PAA scenario, you should have the access to manipulate the main VDD pin/s that feeds the power supply voltage to the core of the chip (not the pad ring). It is recommended in order to get the maximal bandwidth  avaible outside the chip, to mount the attack/analaysis. In a real scenario, this requirement often forces you to cut traces on board or something like that. On the DE0 board, you have no access to the real VDD line, but you can only measure the current absorption before regulators, which implies to work with a significantly smoother bandwidth. Using the DE0 board to do this means violating the warranty on the product. As far as I know, excluding SASEBO/SAKURA boards which are designed to work with PAAs, only STM32 Nucleo boards have an accessible jumper to measure the direct absorption of the chip after the regulator.

    Thanks again for your feedback!

     

    Davide

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