Evaluation of Digital Isolator Eval Kit by ADI

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RoadTest: Enroll to Review the Analog Devices Digital Isolator Eval Kit - MAX2256XAEVKIT#

Author: JWx

Creation date:

Evaluation Type: Evaluation Boards

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: SILICON LABS SI838XISO-KIT ANALOG DEVICES MAX22246CWEVKIT# STMICROELECTRONICS EVALSTISO62XV1

What were the biggest problems encountered?: high headers and jumpers close to the IC mounting place making soldering more difficult

Detailed Review:

Intro

MAX2256x family by Analog Devices consists of four versions of six-channel digital isolators, with varying channel direction distribution: from unidirectional six-channel version (MAX22566), to the balanced three plus three channel one (MAX22563). 

Each version is available in two speed grades, with maximum data rate of 25Mbps or 200Mbps and (being housed in 20-SSOP package with 5.5mm creepage and clearance) is advertised as being able to withstand 3.75kV(RMS) for 60s and 784V(RMS) continously.

With the possibility of powering each side independently from power supply in 1.71V - 5.5V range, it could be deployed as level translator in addition to isolator. 

To evaluate parameters of those isolators, Analog Devices offers an evaluation kit with two versions:

  • MAX22565CA with MAX22565CAAP (5+1 channels) isolator pre-soldered,
  • and unpopulated MAX22565XA, where end user can install precisely the same isolator that is going to be used in the project,

Unboxing

Hardware for roadtest was sent in a shipping box containing two smaller boxes - unpopulated MAX2256XA evaluation kit and IC, allowing for installation of preferred version of the isolator.

{gallery}unboxing

shipping box

upper side

lower side

isolator chip

As a version of isolator provided for testing was MAX22565CAAP+ (200Mbps, 5+1 topology - the same as pre-soldered in MAX22565CA), I  had a chance to build MAX22565CA evaluation kit myself.

Evaluation board has many connectors installed - not only power and ground for both sides of isolator, SMA sockets for signal input and output, but also two headers (named J1 and J2), where most pins of the isolator are available. There are even two additional channels - separated from the rest of the circuit and dedicated for calibration of the test setup. They are consisting of signal track of length that is imposing delay comparable to the passive part of signal patch and can be used to discern how much of the total delay is caused by the isolator and how much by the PCB.

Isolator IC installation

Is it even hand-solderable?

Evaluation kit allows for installation of one of MAX2256x isolators, housed in surface mounted SSOP-20 packages with dimensions as below:

ssop-20

so the question arises if they are at all solderable without a specialized equipment (especially considering distance between pins of 0.65mm). During preparation of test setup, IC in similar (SSOP-14) package was soldered into breakout board that can be bought ready-made from many sources. Photos below detail a process of soldering using a typical, low power soldering iron and magnifying glass (my eyes aren't as good as about twenty years ago):

{gallery}soldering process

IC and PCB

PCB fitting

tinning and removing excess solder

finished

As can be seen, 0.65mm pitch IC can be hand soldered using following steps:

  • PCB should be tinned and flux applied first (it is not given, considering that tinning increase track's height which can make correct positioning more difficult - especially for smaller packages and automatic processes),
  • after correct placement, it is advisable to solder opposite pins at the first step to secure IC in place,
  • excess solder can be removed using desoldering braid,
  • at the end, flux residue can be removed using a flux remover

The same proces was used to populate MAX2256XA kit.

Why not using hot air station? I have decided that the presence of small SMD components near the point of IC installation increases the risk of accidental desoldering them. That risk can be mitigated by use of heat shielding material around the point of installation, but I have decided to give hand-soldering a try.

small SMD components

As can be seen, contacts in the installation area appear pre-tinned, but I had to apply additional solder and flux for soldering.

After some time isolator was installed but the process had it's own difficulties - jumpers and connectors in the area made it more difficult to access soldering points, especially when operating under magnifying glass which limited work field from the above.

soldered chip

As a side note - on the photo above one can see some interesting features of the evaluation board - not only wide separation between sides of different potential but also well-thought layout of signal tracks to equalize their length (and in effect - delay) between channels.

Parameter evaluation

To properly evaluate isolator parameters, test setup was prepared, consisting of:

  • programmable clock generator (SI5351 based),
  • custom daughterboard, piggybacked on J1 and J2 connectors, providing regulated power supply and some measurement circuits.
  • oscilloscope,
  • frequency meter,

block schematics

Custom daughterboard was designed to be fit on the J1 and J2 connectors of the evaluation board, providing power and custom propagation delay measurement circuit.

daughterboard

Basic tests

As of eveluation board manual, initial test was a connection of signal generator and an oscilloscope. First, well formed input:

6MHz input

and resulting output signal

output 6MHz

then something more difficult (as can be seen, our clock generator is not always generating perfect square wave)

input 25MHz

and resulting output - signal was regenerated, we can clearly see that this is a digital (not analog) isolator. In addition, as input signal amplitude has decreased, output fill ratio was also affected (due to the switching threshold of the isolator).

output 25MHz

Power consumption

MAX2256X family provides galvanic isolation using capacitive barrier which offers better parameters than optoelectric solution in both speed and power consumption, but - as it propagates information about state changes - needs additional refresh circuit to reliably transfer slow-changing or constant level signals. Such a circuit usually operates at certain frequency and - given the fact that isolator's power consumption changes  with signal speed - usually sets the minimum power consumption of the chip. To evaluate the power consumption, simple test circuit was prepared. Clock generator was programmed to provide signal of the following frequencies: 100kHz, 1MHz, 6.25MHz, 10MHz, 25MHz and 50MHz (switching in the loop) and was connected to five channels in parallel, then total power consumption (for both side A and B) was measured. Resulting consumption curves were as below

image

Additional curve for 4V was omitted because it was misleading - as we have seen before, our clock generator outputs signal of amplitude slightly decreasing with the frequency, so for 4V there was observable power consumption drop in higher frequencies. That was caused by the fact that input level was similar to the switching threshold of the isolator powered at 4V, resulting in lost cycles and decreased power consumption.

As can be seen from the above graph, power consumption rises with switching frequency and in the 100kHz range is very similar to the idle power consumption, which could indicate that refresh frequency clock is somewhat slower than 100kHz - which is a probable value considering  information from the article from ADI about isolator technologies, where they mention (for different part families) refresh clocks of 1MHz and (after optimization) 17kHz.

MAX2256X datasheet estimates idle power consumption at 0.14mA (input stage) + 0.26mA  (output stage) per channel, which is in line with the measurement, when idle power consumption of the whole (six channel) chip was measured at 2.46mA in the 2-4V supply voltage range.

Similarly, according to the datasheet.  at 3.3V five channels operating at 50MHz should consume 5 * (0.52mA + 0.68mA) and one idle channel 0.4mA, resulting in total consumption of 6.4mA.

As we are measuring not only much greater power consumption, but also different curve shape - more exponential than the expected linear - additional measurement was done, measuring power consumption on both sides separately. Results are as below (side A is an input and side B - output):

image

instead of the expected (from the datasheet)

power consumption curves from datasheet

My hypothesis is that it is caused by the less than ideal input signal shape - we have observed that at higher frequencies our input signal is more triangle than square shaped, so if there is no Schmitt circuit at the input of the isolator (and I didn't find detailed enough description of the inner structure of the chip to verify it), CMOS circuits are known to consume excessive power during slow transition between L and H states, where both transistors can be in (more or less) conducting state at the same time, so that's can be explanation of excessive power draw.

wikipedia CMOS inverter 

Propagation delay

Another interesting parameter is propagation delay and it's skew between channels (that - if excessive - can lead to data errors/race conditions). To measure it, indirect measurement method was used. Using Schmitt-trigger inverter, frequency generator was built and measured delay was put into feedback loop. This way, output frequency was dependent on the sum of two delays: propagation delay of the inverter and measured delay.

generator circuit

Two different inverters were used: standard 74HC14 and high speed 74LVC14. First, propagation delay of the gate and cable of the length similar to the length of connectors needed was measured as a reference.

At 3.3V, 74HC14 used in test was capable of generating 60MHz signal, and 74LVC - 104MHz. Then, frequencies generated when different channels of the isolator was put in the loop were measured:

Measurement results are as in the following table - first for 74HC14 chip, then 74LVC14 (with frequency measured using frequency meter first [mean value of three samples], then using DSO - last series).

Configuration Channel Frequency [Hz] propagation delay [ns]
hc14@3.3V reference 60 000 000 8,33
hc14@3.3V A 22 000 000 14,39
hc14@3.3V B 30 000 000 8,33
hc14@3.3V C 30 000 000 8,33
hc14@3.3V D 30 000 000 8,33
hc14@3.3V E 29 700 000 8,50
hc14@3.3V X 27 700 000 9,72
lvc14@3.3V reference 104 000 000 4,81
lvc14@3.3V A 29 800 000 11,97
lvc14@3.3V B 38 266 667 8,26
lvc14@3.3V C 38 266 667 8,26
lvc14@3.3V D 38 400 000 8,21
lvc14@3.3V E 38 166 667 8,29
lvc14@3.3V X 39 300 000 7,91
lvc14@3.3V osc reference 104 000 000 4,81
lvc14@3.3V osc A 30 850 000 11,40
lvc14@3.3V osc B 35 650 000 9,22
lvc14@3.3V osc C 35 680 000 9,21
lvc14@3.3V osc D 35 920 000 9,11
lvc14@3.3V osc E 35 900 000 9,12

Obtained results were calculated using following formula:

First, propagation delay of the inverter was calculated from the free-running frequency.

Then, total delay of the generator containing measured channel was calculated, from which, after subtracting the inverter delay, estimated channel delay was obtained.

As we can see, results are very good and generally in line with datasheet, which is stating typical propagation delay of 7 ns (at 3V - 3.6V power supply range) with the maximum value of 11 ns - we have measured 8-9 ns.

Another interesting parameter is propagation delay skew - ADI is providing very detailed information about it, including:

  • propagation skew between different parts (using the same channel),
  • propagation skew between channels in the same direction (this one can cause hazard/race conditions when excessive),
  • propagation skew between channels in the opposite directions,

From those three, we were able to verify last two parameters.

As of same direction delay skew: datasheet specifies it at maximum 2ns and we have generally measured less than 0.2 ns (with the exception of channel A - which is exceeding the stated 2 ns at about 2.2 ns - 4 ns).

Opposite direction delay skew - specified as less than 4.9 ns (at 3.3V), was also measured as no greater than about 1 ns, which is very good (also - with the exception of channel A).

As of channel A - given that evaluation kit is an optimized construction, with delay paths equalized between channels - I think that there may be one of two options:

  • either my part is slightly damaged (maybe during transport or soldering/handling),
  • or - given that channel A neighbors with ENA/ENB pins that are shorted by the jumper to Vcc (effectively GND for high frequency signals), maybe some soldering imperfection (for example - some flux residue left after cleaning) is causing additional parasitic capacitance between channel path and GND, thus increasing delay,

In any case - additional tests would need to be done.

Crosstalk

The last test was a try to measure crosstalk between opposite direction channels - in this test, channel in one direction was used in the generator circuit from the last test (switching at about 38MHz with amplitude of 3.3V), and the output of adjacent opposite direction channels was measured (with it's input connected to GND). Following curve was obtained

crosstalk output

but - as some measurement issues were encountered, this test would need to be re-executed if needed. Despite this fact, observed crosstalk is low and could not impede normal operation of the isolator.

Summary

As we have seen, MAX22565 isolator operates as advertised - it is a fast, low power part with low propagation time skew between channels. Evaluation kit is also a good choice - allows for fast and easy initial evaluation of the chip, but for complete beginners, maybe pre-soldered version could be more fitting.

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