RoadTest: Apply to test a Microchip Curiosity Nano Development Board
Author: neerajrd82
Creation date:
Evaluation Type: Evaluation Boards
Did you receive all parts the manufacturer stated would be included in the package?: True
What other parts do you consider comparable to this product?: PIC16F13276,PIC18F-Q35, EFM8LB1
What were the biggest problems encountered?: The biggest problem encountered in firmware ->Peripheral Pin Select (PPS) Configuration is not clearly written for some peripharals. There are no physical mechanical switches or cut-straps standing between the level shifters and Port C. The debugger's level-shifter outputs are permanently tied to these traces. If your target firmware attempts to use RC4 or RC5 to talk to an external sensor while a terminal program on your PC is holding the USB connection open, the level shifters will actively fight your external sensor, resulting in corrupt data packet errors. there is no provision of manual hard reset.
Detailed Review:
1. Unboxing and First Impressions: Hardware Readiness
The image illustrates the unboxing of the Microchip EV06M52A Curiosity Nano Evaluation Kit from its distinct red "Development Tools" packaging. The kit arrives with the main development board and two detached 14-pin berg strip headers. Because a USB Type-C cable is not included in the retail box, developers will need to supply their own to power and interface with the unit.
The evaluation kit is cleverly designed to accommodate two entirely different debugging workflows:
Internal Debugging (Ready Out-of-the-Box): The board features an on-board PICkit On-Board 4 (PKOB4) programmer and debugger seamlessly connected to the target PIC16F13145 microcontroller. For standard evaluation, firmware development, and testing of the internal Configurable Logic Block (CLB), no soldering is required. You can interact with the target MCU immediately via the USB-C port.
External Debugging & Extension (Requires Assembly): The two included berg strips are provided for optional expansion. If you need to route signals to a breadboard, interface with external target chips, or use the on-board debugger to program an external MCU, these headers will need to be permanently attached to the board using a soldering iron.
2. Microchip EV06M52A Curiosity Nano Evaluation Kit connected with Windows 10 PC
Upon connecting the EV06M52A Curiosity Nano Evaluation Kit to a Windows 10 machine, the plug-and-play convenience of the platform is immediately apparent. The on-board debugger automatically configures the necessary drivers and enumerates as a standard USB Mass Storage Class (MSC) device after loading MPLAB-X-IDE & IPE. As shown in the system explorer, it successfully mounts a virtual flash drive labeled CURIOSITY. This Mass Storage functionality is an excellent workflow feature; not only does it quickly confirm that the host PC recognizes the hardware, but it also allows developers to flash the PIC16F13145 simply by dragging and dropping compiled .hex files directly onto the drive, entirely bypassing the need to open a heavy IDE for rapid firmware updates.
3. Device Enumeration & Connectivity shown in Device manager in windows 10
A quick look at the Windows Device Manager confirms that the EV06M52A Curiosity Nano utilizes a well-designed composite USB configuration. Upon connection, the on-board debugger (PKOB4) automatically enumerates and exposes three distinct interfaces, each serving a critical development function:
Microchip Tools: This entry represents the primary hardware debugger interface. It allows the MPLAB X IDE to seamlessly connect to the board, enabling full-speed programming, single-stepping, and in-circuit debugging of the PIC16F13145.
USB Serial Device (COM Port): The board includes a built-in Virtual COM Port (CDC) bridge—in this instance, mapped to COM3. This is a highly convenient feature that links the target MCU's UART directly to the host PC. It eliminates the need for external FTDI cables or serial adapters when monitoring console output or sending serial commands.
USB Mass Storage Device: This interface drives the drag-and-drop programming functionality. By enumerating as a mass storage device, the board can mount the "CURIOSITY" flash drive, allowing developers to program the target controller by simply copying a compiled .hex file directly over to it.
This composite approach ensures that power, debugging, programming, and serial communications are all handled elegantly through a single USB Type-C connection.
4. Toolchain Integration: Connecting via MPLAB IPE
To verify the programming interface and hardware communication independently of the main development IDE, I launched the MPLAB Integrated Programming Environment (IPE) v6.30. The software quickly recognized the board's on-board debugger as a "PKOB nano" tool.
Upon initiating the connection to the target PIC16F13145, the output console provided a clean and successful initialization sequence. Breaking down the connection log reveals several key operational details:
Device Pack Initialization: The environment automatically identifies and utilizes the correct Device Family Pack (PIC16F1xxxx_DFP, 1.29.444), ensuring the latest programming specifications are applied to the target.
Target Power Delivery: The log explicitly confirms that the PKOB nano is actively supplying power to the target MCU at 5.00 volts (PKOB nano is supplying power to the target (5.00 volts)). This verifies that the on-board regulator is functioning correctly, allowing for immediate bench testing without any external bench supplies.
Silicon Verification: The API successfully executes the read commands to query the configuration memory. It accurately detects the target device as the PIC16F13145, returning a Device ID of 0x3129 and a Revision ID of 0x2003.
Overall, the MPLAB IPE demonstrates stable, error-free communication with the Curiosity Nano right out of the gate. The hardware handshake is seamless, establishing a highly reliable foundation for flashing custom .hex binaries throughout the rest of this evaluation.
5. Memory Erase and Target Reset Control
To ensure a completely clean slate before flashing custom firmware, I executed a full device erase using the MPLAB IPE. Testing the erase function is a great way to verify that the on-board PKOB nano debugger has full read, write, and wipe authority over the target PIC16F13145 without any protection faults.
The console output from this operation highlights a few excellent automated features of the Microchip toolchain:
Intelligent Config Restoration: The log shows that immediately following the bulk Erase command, the API writes 10 bytes to the Configuration Memory (address 0x01000E). This is a critical safety mechanism; the tool automatically restores default configuration bits (such as debug enable and oscillator settings) so the chip does not accidentally lock you out or enter an unrecoverable state after a wipe.
User ID Management: The sequence also writes 8 bytes to the User ID memory space (0x010000). For developers planning to take this silicon into production, having easy IDE access to write version control or serial numbers directly to the ID space is highly convenient.
Hardware Reset Control: The log concludes with the message *** Hold In Reset mode is enabled ***. This demonstrates that the PKOB nano actively controls the target's reset line (MCLR). Holding the chip in reset after programming or erasing is a vital debugging feature, as it prevents the microcontroller from immediately attempting to execute code or driving pins high before the developer manually releases it.
Overall, the erase sequence was rapid, and the IPE handled all the necessary memory boundaries and configuration restorations seamlessly behind the scenes.
6. Firmware Deployment: Flashing the Application
With the board successfully communicating and erased, the next step was to validate the core toolchain workflow by flashing a standard baseline application. Using the MPLAB IPE, I loaded a compiled blinky.hex binary and initiated the programming sequence.
The console output provides an excellent, transparent view of how the PKOB nano handles the deployment of the firmware to the PIC16F13145:
Automated Preparation: Upon starting the programming operation, the IPE first calculates the required memory ranges based on the hex file and executes a fresh bulk Erase command. This ensures no residual data conflicts with the incoming firmware.
Target Memory Allocation: The log clearly details exactly where the code is being mapped:
Program Memory (Flash): The toolchain writes 768 bytes starting at address 0x000000 up to 0x17f. This tiny footprint is exactly what you would expect for a highly optimized "Blinky" application on an 8-bit PIC architecture.
Configuration & ID Spaces: Alongside the main application code, the programmer seamlessly writes 10 bytes to the Configuration memory (0x01000E) and 8 bytes to the User ID memory (0x010000). This ensures all oscillator settings, watchdog timers, and developer ID tags are perfectly synced with the flashed code.
Controlled Execution: Just like the erase operation, the programming sequence concludes by returning a Programming complete status and immediately enabling the *** Hold In Reset mode ***. This is a fantastic safety feature for hardware testing, allowing the developer to attach probes or prepare a test setup before manually releasing the MCU to execute the newly flashed code.
Overall, the deployment was swift and flawless. The IPE and PKOB nano handled the address parsing and memory writing seamlessly, proving that getting code onto the Curiosity Nano is a highly reliable, frictionless process.
Update on 10/06/2026 after performing some test on various peripherals are given below:
7. GPIO OUTPUT Test is given below: 
this is the firmware which was developed using MCC for GPIO OUTPUT but some part was manually written by me to check the reliability of target chip.
That confirms several things:
8. GPIO INPUT Test is given below:
this is the firmware which was developed using MCC for GPIO INPUT but some part was manually written by me to check the reliability of target chip.
That confirms several things:
9. EUSART Test is given below: 
this is the firmware which was developed using MCC for EUSART but some part was manually written by me to check the reliability of target chip.
That confirms several things:
In above screenshot, COM PORT toolkit has been shown where some ascii characters has been transmitted & received by same using loopback method inside EUSART of PIC.
10. PWM Test is given below: 
this is the firmware which was developed using MCC for PWM but some part was manually written by me to check the reliability of target chip.
That confirms several things:
11. ADC Test is given below:
this is the firmware which was developed using MCC for ADC but some part was manually written by me to check the reliability of target chip.
Notable point is example given on datasheet which makes our understanding better about ADC inside PIC16F13145.
Another point to noted that MCU pin other what is mentioned in example needs to be configured for better performance.
Now, above confirms the following points.
11. DAC Test is given below:
this is the firmware which was developed using MCC for DAC but some part was manually written by me to check the reliability of target chip.
Notable points is only 2 registers are need are to be configured for DAC, which actually introduces the simplicity in firmware.
As it can seen that DAC is programmed to generate the pulse delibrately to check the linearity of analog output as shown in commonly available low cost salae logic analyser.
Now, above confirms the following points.
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12. Schematics Analysis is given below:
When analyzing the target microcontroller schematic block of the EV06M52A Evaluation Kit, we must isolate the raw electrical connections from the flawed, legacy text templates embedded in the design files. Below is the verified hardware-to-firmware breakdown.
The physical allocation of the key pins used during design verification maps as follows:
RC2 (PWM Output / Yellow LED): Labeled as LED0, it is connected directly to the on-board yellow user LED through a current-limiting resistor. It is wired in an active-high configuration (sourcing current from the MCU to GND).
Firmware Mapping: Must be driven by a digital push-pull stage via Peripheral Pin Select (PPS) code RC2PPS = 0x2C; (PWM1_OUT).
RC3 (Analog Input / Mechanical Switch): Labeled as SW0, it connects directly to the tactile user push button. Mechanically, pressing the switch dead-shorts the RC3 trace to GND. Crucially, there is no external physical pull-up resistor on this net.
Firmware Mapping: The internal Weak Pull-Up register must be explicitly enabled in your code (WPUCbits.WPUC3 = 1;) to keep the line from floating when the button is released.
RA2 (Analog Output / DAC Breakdown): Labeled purely as a pin header breakthrough on the outer edge footprint. There are no on-board loads or decoupling filtering networks attached to this track, preserving it entirely as an unadulterated analog channel mapping to DAC1OUT2.
Firmware Mapping: Requires TRISAbits.TRISA2 = 1 and ANSELAbits.ANSELA2 = 1 to disable the digital buffer overrides, allowing the 8-bit DAC1DAT register to smoothly drive physical hardware.
A detailed review of Figure 11-1 (Clock Source Block Diagram) in the PIC16F13145 family datasheet reveals that the internal 4x PLL block is fully accessible by the External Oscillator (EXTOSC) module via an input multiplexer. This opens up two distinct pathways for utilizing external components to achieve the maximum hardware execution speed of 32MHz.
While classic PIC architectures often utilized a 2x PLL paired with a 16MHz crystal, the PIC16F13145 utilizes a fixed 4x PLL.
If a 16MHz crystal were routed through this 4x PLL, the clock tree would attempt to output an unstable 64MHz (16MHz×4), violating the absolute electrical operating limits of the microcontroller core.
The Solution: To achieve a precise 32MHz system clock (FOSC) using a passive external crystal, you must source a 8MHz Crystal (8MHz×4=32MHz) configured in HS (High-Speed Crystal) Mode.
The yellow note text on the Curiosity Nano board stating "Crystal datasheet: Ccrystal=9pF... Selected in design after verification C=12/12pF" contains a structural naming error. In standard electrical engineering syntax, 9pF represents the target Load Capacitance (CL), not a physical component value.
The layout populates two physical 12pF ceramic loading capacitors (C1 and C2) to ground. Factoring in an average parasitic board stray capacitance (Cstray) of ∼3pF on this compact layout, the network yields:
The Takeaway: If you choose to bypass the internal 32MHz oscillator to gain the tight tolerances of external hardware, you must source an 8MHz crystal specified with an explicit 9pF Load Capacitance (CL). Sourcing a crystal with a native 9pF internal shunt or structural specification will cause frequency drift or startup stagnation.
Based on the validated clock tree architecture, you have three distinct methods to clock the device at maximum speed:
Method A (Default Internal): Natively using the internal HFINTOSC configured to 8MHz and scaled by the internal 4x PLL block to output 32MHz. This requires zero external hardware and matches the out-of-the-box state of the Curiosity Nano board.
Method B (External Passive Crystal + 4x PLL): Solder a 8MHz crystal (CL=9pF) across the open X100 layout pads (RA4/RA5). Note that the text box mistakenly references a 32.768kHz RTC footprint style; for a primary clock source, the layout tracks map straight to the edge headers without isolation barriers.
Method C (External Active Clock Source): Inject a raw, active 32MHz CMOS digital square-wave oscillator signal directly into CLKIN (RA5) using EC Mode, which bypasses the PLL completely.
If you implement the recommended 8MHz external crystal to achieve a 32MHz system speed, update your configuration bits and initialization routines as follows:
// Configuration Bits Configuration for 8MHz Crystal + 4x PLL = 32MHz
void CLOCK_Initialize_External(void)
{ // Enable the External Oscillator module OSCENbits.EXTOEN = 1;
// Wait for the External Crystal and PLL to lock and stabilize while(!OSCSTATbits.EXTOR);
// Wait for EXTOSC to be ready while(!OSCSTATbits.PLLR); // Wait for 4x PLL to be stable
}
The Limitation: The EV06M52A schematic features no provision for a physical, mechanical reset switch (such as a tactile push-button) connected to the target MCU's master reset line (MCLR / Pin RA3).
The Circuit Mechanism: The MCLR pin is tied to the VCC_TARGET rail via a standard pull-up resistor and is routed directly through a level translator to the on-board debugger microcontroller. Consequently, the reset state of the PIC16F13145 is under absolute, centralized software control by the nEDBG system.
Impact on Development & Testing: * To force a hardware reset during prototyping, you cannot simply press a button on the board. You must either click the "Reset" icon inside MPLAB X IDE (which instructs the debugger chip to pull the MCLR line low digitally) or completely power-cycle the USB-C connection.
If the board is disconnected from a PC terminal and running autonomously from an external USB power bank, a manual hardware reset is impossible without physically unplugging the power source.
If your testing workflow strictly requires a physical, manual reset button, the schematic shows that the MCLR (RA3) net is broken out to the edge connector header. You can easily implement a manual reset by wiring an external tactile switch between the MCLR edge pin and GND:
When pressed, this external switch will safely pull the MCLR line to 0V, overriding the debugger's pull-up and forcing a clean hardware reset without disrupting your USB debugging session.
The debugger architecture relies on an independent, high-performance microcontroller (typically a 32-bit ATSAMD21 or similar Cortex-M0+ variant) running custom factory firmware. It handles three core responsibilities: Virtual COM Port (CDC) bridging, In-Circuit Serial Programming (ICSP), and Variable Power Supply regulation.
Because the debugger is designed to support target MCUs running anywhere from 1.8V to 5.5V, it cannot connect its native 3.3V I/O pins directly to the PIC16F13145.
The Hardware: Look for a series of small, multi-pin ICs labeled as level translators (typically devices like the 74LVC1T45 or 74LVC2T45 dual-supply bidirectional buffers).
The Circuitry: One side of these level shifters is powered by the debugger's native VCC_DEBUG (3.3V), while the other side is powered by VCC_TARGET (the voltage currently feeding your PIC).
The Constraint: These level shifters introduce small propagation delays and input capacitances. This is exactly why the programming lines (ICSPCLK and ICSPDAT) have high capacitive loading on the board, making them poor choices for high-speed external digital communication in your custom code.
The debugger presents itself to your computer operating system as a standard USB Class 2 Communications Device (CDC).
The Net Traps: Trace the nets labeled CDC_TX and CDC_RX away from the debugger MCU. They pass through the level shifters and connect directly to your target chip's RC5 and RC4 pins, respectively.
The Design Consequence: There are no physical mechanical switches or cut-straps standing between the level shifters and Port C. The debugger's level-shifter outputs are permanently tied to these traces. If your target firmware attempts to use RC4 or RC5 to talk to an external sensor while a terminal program on your PC is holding the USB connection open, the level shifters will actively fight your external sensor, resulting in corrupt data packet errors.
One of the most complex sub-blocks in the debugger section is the target power generation circuit.
The Regulator: The board utilizes an adjustable low-dropout (LDO) regulator, typically the MIC5353 or equivalent.
The Control Loop: The debugger MCU generates a precise internal analog voltage (via its onboard DAC or a heavily filtered high-frequency PWM stream) and feeds it into the reference/adj pin of the MIC5353 regulator.
The Result: This gives MPLAB X IDE total software control over the target power rail. When you change the voltage slider in your project properties from 3.3V to 5.0V, the debugger micro alters its analog output, shifting the VCC_TARGET rail dynamically. This is very unique feature by microchip.
Look closely at the status LED tied to the debugger microcontroller (usually a green or red LED labeled LED1 or STATUS).
Hardware Polarity: Note how the debugger MCU drives this LED. If the debugger chip crashes, hangs, or drops its USB connection enumeration with your PC, this LED will pulse in specific diagnostic blink patterns (e.g., rapid flashing indicates a USB enumeration error or a short-circuit condition detected on VCC_TARGET).
This table summarizes how the debugger pins explicitly bind to your target environment across the isolation barrier:
By physically slicing the thin copper bridge on the J200 / J201 Cut-Strap, you completely decouple the on-board variable LDO regulator output from the target PIC16F13145's VDD rail. This state of absolute isolation allows for two advanced bench-testing configurations:
If you are integrating the Curiosity Nano board into a larger system prototype that has its own regulated power bus (e.g., a stable external +5V or +3.3V system rail), you can slice the cut-strap to prevent the on-board debugger's LDO regulator from fighting your external system supply.
You feed your external system power directly into the VTG (Target VCC) edge header pin.
This safely runs the target PIC16F13145 from your external power architecture while keeping the on-board debugger completely alive over USB-C for real-time firmware flashing and step-by-step debugging.
Because the level shifters for the programming bus (ICSPCLK, ICSPDAT, and MCLR) match their voltage logic levels to whatever voltage is present on the target side of the cut-strap, cutting the strap allows you to hijack the nEDBG debugger to program a completely separate, external PIC microcontroller on a breadboard.
[On-Board nEDBG Debugger Chip]
|
(ICSPCLK / ICSPDAT / MCLR / VCC_DEBUG)
|
[Dual-Supply Level Shifters]
|
+------------------------+------------------------+
| |
[J200/J201 CUT-STRAP] [EDGE HEADERS]
(Sliced / Open Circuit) |
| (Wires to Breadboard)
[Target PIC16F13145] |
(Dead / No Power Supply) [External PIC Microcontroller]
(Fully Powered & Programmed!)
The Execution: Slice the J200/J201 copper trace. Leave the target side of the strap unpowered—this completely cuts power to the on-board PIC16F13145, dropping it into a "dead" high-impedance state so its pins don't interfere with your project.
The Interface: Run jumper wires from the Curiosity Nano's edge pins (MCLR, CLK, DAT, GND, and VCC) to the corresponding ICSP programming pins on your external target PIC microcontroller.
The Result: When you click "Program" in MPLAB X IDE, the debugger will pass the code straight through the edge headers and flash your external target micro flawlessly. This effectively turns your $15 evaluation kit into a fully functional, universal Microchip PICkit programmer!
The power supply infrastructure is split into two primary domains: the Debugger Power Domain (fixed at a steady 3.3V) and the Target Power Domain (variable from 1.8V to 5.5V). This isolation ensures that even if you short-circuit your target microcontroller project during an experiment, the on-board USB debugger chip remains protected and online.
Power enters the board exclusively through the USB-C connector via the VBUS rail (nominally +5V from the PC host).
The Protection Network: Look for a low-forward-voltage Schottky diode (often labeled as a PRTR5V0U2X ESD protection array or a standard clamping diode) and a resettable PTC fuse inline with VBUS. This network clamps high-voltage static transients (ESD) from your hands and limits maximum current draw to prevent tripping your PC’s USB port protection.
The Split: The raw VBUS rail splits immediately after the protection stage:
One branch routes directly to a fixed 3.3V regulator to power the debugger subsystem (VCC_DEBUG).
The second branch routes to the input of the adjustable target regulator to create VCC_TARGET.
The centerpiece of the target power rail is an adjustable, high-accuracy Low-Dropout (LDO) linear regulator (typically the MIC5353 or equivalent).
The Reference Control Loop: Unlike a standard fixed regulator, the reference/adjust pin of this LDO is driven by a smoothed, low-pass filtered PWM signal or a direct DAC output originating from the debugger microcontroller.
Dynamic Voltage Scaling (DVS): When you alter the voltage settings inside the MPLAB X IDE project properties, the debugger changes the analog control voltage on the regulator's adjust pin. This shifts the output on the VCC_TARGET rail dynamically between 1.8V and 5.5V.
The Linear Constraint: Because this is a linear regulator, any voltage drop is dissipated purely as heat. If VBUS is 5V and you configure your target code to run at 1.8V for low-power benchmarking, the regulator drops 3.2V across its internal pass transistor. Keep your current draw minimal at lower voltages to avoid thermal throttling.
Look closely at the schematic net connecting the output of the variable regulator to the target MCU's $V_{DD}$ pins. You will find an intentional break in the PCB copper trace labeled as a Cut-Strap or Jumper Header (J200 / J201).
Out-of-the-Box State: From the factory, this break is shorted out by a tiny, thin copper trace embedded directly into the circuit board layout, allowing power to flow seamlessly.
Amperage Benchmarking: If you need to measure the precise power consumption of your PIC16F13145 firmware (such as validating low-power Sleep modes), you must take a hobby knife and physically slice the thin copper trace between the pads.
The Measurement Circuit: Once cut, the circuit is open. You must connect a digital multimeter (configured to measure μA or mA) or a specialized current optimization tool across the header pins to bridge the gap and measure true inline current consumption.
This engineering matrix details how power distributes across the layout of the EV06M52A board:
13. Conclusion:
This technical audit of the Microchip EV06M52A (PIC16F13145 Curiosity Nano) Evaluation Kit confirms that the board is a highly integrated, robust prototyping platform, provided the developer accounts for several critical hardware-to-documentation mismatches. By peeling back the layers of the official schematics and user guides, this evaluation bridges the gap between errant documentation templates and the physical realities of the copper layout.
Analog & Digital Peripheral Integrity: Initial firmware development exposed classic configuration traps. Successful EUSART loopback tracking requires strict adherence to the true input/output structure of the Peripheral Pin Select (PPS) network (RX1PPS = 0x15). Furthermore, the active-high Yellow LED (LED0) on pin RC2 and the mechanical switch (SW0) on pin RC3 demand precision register initializations—specifically handling the master ANSELC digital buffer overrides and enforcing the internal Weak Pull-Up (WPUCbits.WPUC3 = 1) due to the complete omission of external physical pull-up resistors on the board.
The Oscillator Circuit Error: A major achievement of this audit was uncovering and correcting the critical text blunder in the unpopulated external crystal (X100) layout notes. While the official documentation references an errant "Ccrystal=9pF" value and suggests a legacy 16MHz/2x-PLL configuration, hardware tree verification via Datasheet Figure 11-1 proves that the internal 4x-PLL must be paired with an 8MHz passive crystal specified for an explicit 9pF Load Capacitance (CL) to safely achieve the maximum 32MHz system operating frequency (FOSC).
The on-board nEDBG architecture provides exceptional developmental agility through software-controlled variable power regulation (1.8V−5.5V) via the MIC5353 LDO loop. However, this introduces power rail fluctuations that mandate utilizing the target MCU’s internal Fixed Voltage Reference (FVR) for high-precision ADC and DAC waveforms.
Developers must also remain cognizant of the lack of a physical manual reset switch on the board, requiring reset commands to be issued strictly via the host IDE or through an external mechanical workaround wired to the MCLR edge header.
Beyond its documented evaluation features, the physical separation of the power domains via the J200 / J201 Cut-Strap transforms the commercial utility of this kit. Slicing this integrated trace isolates and silences the native PIC16F13145, effectively turning the evaluation board into a low-cost, universal In-Circuit Serial Programmer (ICSP) capable of flashing and debugging external PIC microcontrollers directly on a breadboard or custom production PCB.
The EV06M52A is an outstanding tool for evaluating the PIC16F13145 family and its specialized Configurable Logic Blocks (CLB). Now that the physical layout constraints, true pin mappings, and clock tree architectures are thoroughly mapped and audited, this platform is fully optimized to serve as a reliable blueprint for rapid, production-grade embedded hardware and firmware development.
Legend: Text with red font with yellow background highlights negative points.
Text with Green font with yellow background highlights positive points.
My sincere thanks for element 14 community team & Microchip who have sponsored this kit & favourably looked upon me for feedback.
