AVNET MiniZed Dev Board - Review

Table of contents

RoadTest: AVNET MiniZed

Author: xgelectro

Creation date:

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: Digilent Zybo (Xilinx Zynq 7010 ; FPGA + 2x Cortex A9) Digilent Arty (Xilinx Artix 7 ; FPGA only)

What were the biggest problems encountered?: null

Detailed Review:

Preliminary note :

This roadtest isn't totally finnished. It will be done when I'll have a bit spare time.

A small list of what will be added shortly is available at the bottom.

Index

  • Introduction
  • Unboxing
  • Preinstalled demo
  • Documentation
  • First scratch hardware project (PL)
  • Software Hello World bare-metal Project (PS)

 

Introduction

The MiniZed development board is built around the Xilinx Zynq 7Z007S device, which is an SoC including :

  • The PS part : A single-core ARM® Cortex™-A9
  • The PL part : An FPGA (14400 LUTs ; 28800 FFs ; 1.8Mb RAM : 66 DSP slices).

There are configurable interconnections between them, allowing the CPU to access peripherals designed in the FPGA through AXI buses.

 

This board is one of the cheapest with such an SoC, and offers Arduino and PMOD connectivity.

 

 

Despite its small form-factor, the board has an interesting set of memory and devices :

  • 512MB DDR3L
  • 128Mb QSPI flash
  • 8Gb eMMC flash
  • Onboard JTAG programmer with an UART channel
  • A Murata 1DX module providing Wi-Fi b/g/n through SDIO and Bluetooth 4.1 via UART
  • MEMS Sensors : Motion & Temperature (ST LIS2DS12) and Microphone (ST MP34DT05)
  • An USB Host PHY
  • 2 bi-element LEDs (one wired to the PL part, and the other to the PS part)
  • 1 Pushbutton wired to the PS part and a Reset pushbutton

 

There are 16 GPIOs available through the 2 PMODs connectors. The signals are wired as differential pairs and could be used as TMDS I/Os or LVDS inputs only (because of the 3.3V on the IO banks). I haven’t checked for the other differential IO standards.

Another 22 GPIOs are available on the Arduino connector but 3 of them are shared with PL LEDs and a switch. The analog pins are wired to the internal XADC (not tested)

 

Unboxing

The box contains :

  • The MiniZed
  • Micro USB cable and 3 jumpers (although the board doesn’t need any jumper)
  • A Quick Start guide for the preloaded demo
  • Safety Instructions
  • A Voucher for SDSoC

 

Preinstalled demo

Once the board is connected, the CPU will start U-Boot. Then U-Boot will load the configuration to the FPGA, the kernel, the devicetree and the ramdisk to RAM and then boot the kernel.

The system booted is named PetaLinux which is a branch of Yocto and customized by Xilinx.

The console is available through the USB JTAG+UART with the following settings : 115200 bauds, 8 data bits and 1 stop bit.

A few commands are discussed in their Getting Started Guide to test sensors, WiFi and Bluetooth

The FPGA part is loaded with a demo which make a led blinking and showing sounds received by the microphone

 

Documentation

At the time of writing, documentation is available at these links :

The documentation is very complete with schematics, getting started, tutorials, files needed for design, BSP, factory images, …

 

First scratch hardware project (PL)

The Vivado environment is available for download there : https://www.xilinx.com/support/download.html
You’ll need to install the SDK and the Zynq7000 support.

 

For the project, we will need the Constraints File and the Board Definition Files (only with Vivado < 2017.4) which are available here : http://zedboard.org/support/documentation/18891

The installation instructions for the Board Definition are included in the ZIP file, and the Constraints will be added later in the project.

 

The new project

We will first start by creating a new project.

I did it on Windows, I would suggest you to think about avoiding long path lenght and spaces in path or filenames.

I haven't checked if there is any problems with paths, be it's better to be sure from the beginning.

Starting with Vivado 2017.4, the needed Board Definition Files are already included, otherwise you would have to install it manually. The installation instruction is included in the ZIP file available on the zedboard.org website.

Now the project is created and the workspace is shown.

 

On the left, there are shortcuts for the project realisation flow :

  • Source / Project creation / Block Design (Project Manager / IP Integrator)
  • Simulation
  • RTL Analysis which is in short to check the translation of the code to logic blocks and wiring
  • Synthesis which translate your code in blocks ready to be allocated to FPGA ressources (may depends on block design generation if used)
  • Implementation which will place the logic functions and route them onto the FPGA (depends on synthesis)
  • Program and Debug
    • Generate Bitstream which generate the binary file to be loaded on the FPGA (depends on implementation)
    • And the tools to program and debug designs

 

The project summary is an interresting page, which will display Timing, Utilization and Power informations of your design once it will be implemented.

 

 

Creating a new block design

We will now create a block design which will be the top element of the hierarchy.

I did this just to be able to use a clock given from the PLL of the PS part.

On this board there ISN'T any clock directly connected to the PL part. So we have to use one coming from the PS.

 

So to start a new block design, just click Create Block Design on the left bar.

Once it's created, the BD (Block Design) is empty. To add a new block just click on the cross.

Then select ZYNQ7 Processing System (the search feature will help you to find it easily among every available IP Cores.

Design Assistance is suggested, so click on Run Bock Automation it will start a small pre-configuration wizzard for the block.

Here, select Apply Board Preset which will apply the configuration given in the Board Definition Files and connect some interfaces.

If you make a double-click on the block, you'll get a window to reconfigure the IP Core. Here, we can see the two clocks made available to the PL part and their frequencies.

I didn't changed anything it was just to check the clocks.

 

 

 

Adding the Constraints file

I copied the constraint file downloaded from the zedboard.org website to the project folder and added it to the project via the Start by clicking on Add Source button, then selecting Add or create constraints.

The constraints give informations for the implementation such as the nets names/pins association, IO standards, clock constraints, etc.

 

 

Creating a Verilog module

Now we will make a module written in Verilog which will be added to the BD later.

Start by clicking on Add Source, then select Add or create design sources.

Then create a Verilog file, I named mine "blink_led".

Once the file is created, the wizard propose to add inputs and outputs to generate a base template.

Some useful templates are available. To open them, click on Language Templates on the left bar.

Here is my code for the blink_led module. It will toggle the led output each time the counter will arrive at 50.000.000 which will give us a 1sec ON / 1sec OFF led output with the 50MHz clock.

Adding the Verilog module to the block design

Now we will add the module to the BD with a simple right-click in the BD, the Add Module. Availables modules will be displayed, you'll just have to choose the correct one.

Once the module is added, connect the clock then right-click on the led pin and select Make External it will connect it to an output of the BD.

Creating the Top Level of the design

A block design isn't directly synthesizable code, so we have to Create an HDL Wrapper and set it as the Top level module.

 

Bitstream generation (Synthesis + Implementation + Bitstream generation)

Now we can save everything and click on Generate Bitstream in Program and Debug. It will automaticaly generate the block design, then proceed to synthesis, implementation and bitstream generation.

Once the generation is done which will take more or less time depending on the build machine, select Open Hardware Manager.

 

 

FPGA Programming

As currently no target is opened, it will suggest you to open one. The Auto Connect function works correctly but I don't know its limitations besides the fact it will use a JTAG clock of 15MHz while 30MHz also works.

Then you can click on Program device on the green suggestions bar, otherwise with a right-click on the target device.

Final note

This project depends on the Zynq subsystem (PS part) and while experimenting, I found that there isn't any clock if the CPU isn't started.

So we will create a Hello World project to be complete.

 

Software Hello World bare-metal Project (PS)

Workspace creation

The SDK will need some informations such as peripherals configuration, etc.

So we are going to create them before launching the SDK.

Select Include bitstream as it will be easier in the SDK to program the FPGA later.

Now, launch the SDK from Vivado.

And here it is, showing the Hardware Platform Specs.

 

 

Project creation

Now, we can create our Hello World project.

Click on File -> New -> Application Project.

Then choose a name for the project and let the SDK automatically generate a BSP project.

Now we have an Hello World project created with sample source code and a BSP.

 

 

BSP Configuration

By default, the STDIO is set to UART0. However on the MiniZed, this is the UART1 which is connected to the USB to JTAG+UART bridge.

So we will set the STDIO settings correctly in the BSP.

In the system.mss file, click on Modify this BSP's Settings.

Then in Overview -> Standalone, select ps7_uart_1 for stdin and stdout.

 

 

Debugging

Now we can setup a debugging configuration.

Click on Run -> Debug Configurations.

A double-click on Xilinx C/C++ application (System Debugger) will create a basic configuration.

You'll have to select Standalone Application Debug and check Reset entire system. The last one is to be sure te whole system (PS+PL) is reset.

Then in the Application tab, check Download to make the debugger upload the program to the PS while starting.

You can now apply the configuration and click on Debug.

The FPGA is reset, PS and PL part are programmed and the program is waiting at the entry of main(). To continue, just press the "play"-like button.

You can see the 'Hello World" string printed on the serial port at a baudrate of 115200.

 

Not yet finished

Yet to come :

  • Debian installation on eMMC
  • A conclusion
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