Avnet Ultra96 Dev Board - Review

Table of contents

RoadTest: Avnet Ultra96 Dev Board

Author: cmelement14

Creation date:

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: Ultra96 dev board probably is the lowest cost development board for Zynq UltraScale+ device currently on the market. It's hard to find comparable products at such a low cost.

What were the biggest problems encountered?: I didn't have any big problem with the board itself, but I couldn't get the newer version BNN image classification example work (i.e., 2018.1 Image for AIC Demo for ZCU102 and Ultra96). Fortunately I can get the old version work which I will describe in the second part of my review.

Detailed Review:

Ultra96 Dev Board for Automotive Application



First of all, thank Randall Scasny() for organizing this Avnet Ultra96 Dev Board road test and Avnet for offering the road test kit. I am very grateful for being selected for the road test.


Zynq UltraScale+ device is a very powerful and versatile device. It integrates both FPGA and ARM multi-core microprocessors into one SoC package. Zynq UltraScale+ is targeted for a variety of applications such as network, video process, medical, IoT, automotive application, etc. In this review, I will demonstrate a couple of examples for automotive application on Avnet Ultra96 Dev Board. The first example is regarding the fundamental of automotive application - CAN communication. I will add an off-board CAN transceiver to Ultra96 and enable CAN capability on the Cortex-R5 cores. The second example demonstrates a basic autonomous driving capability - road sign image classification which is based on this Xilinx wiki article.



Part I - CAN Communication Example


1. Prerequisite


To follow the steps in this review, I assume you have some background about the following topics: CAN communication, Xilinx Vivado, Xilinx SDK. You also need the following hardware and software:

1. CAN transceiver (may also need level shifter). I used a low cost SN65HVD230 CAN board from Waveshare and a level shifter chip MAX13003E.

2. A CAN bus tool which can monitor CAN bus traffic. I used Vector VN1630A which is very pricey. There are some low cost alternatives listed in this article.

3. Xilinx Vivado 2018.2 Software for creating the hardware platform.

4. Xilinx SDK 2018.2 Software for creating the BSP and the application.



2. Bring out 3.3V


The SN65HVD230 CAN board needs 3.3V power input and there's no 3.3V on Ultra96's connectors. I found one end of C37 is connected to 3.3V, so I soldered a wire and brought 3.3V to my breadboard as shown in the following photos. Since C37 is on the bottom side of the PCB, we need to unscrew the four screws on the top side in order to access C37's pin.






Connect the level shifter and SN65HVD230 CAN board together on the breadboard as shown below. Please note, you also need to connect a 120 Ohm termination resistor between the pair of CAN wires going to the CAN bus tool. Make sure the CAN wire's polarity is correct, i.e., positive is connected to positive and negative is connected to negative.




3. Add CAN Interface to the Hardware Platform


Using Zynq device is slightly more complicated than regular microcontrollers. Before you can create a software project for your application using Xilinx SDK, a hardware platform has to be created using Xilinx Vivado. I assume you have some hands-on experience on Vivado software, otherwise, please refer to Xilinx documentation.


First, you need to create a base system and add a Zynq UltraScale+ MPSoC IP block into your design as shown below.



Next, you need to customize the added IP block to include a CAN interface. Right click on the IP block name then choose Customize Block... menu item.



In the customization pop-up window, click on CAN1 block as highlighted below. A check box should add to the right hand side of the CAN1 label and an IO configuration window should also pop up. 



In the IO configuration window, make sure CAN1 is checked. Also choose MIO 36 ... 37 as IO pins from the pull-down list as shown below. Then click OK and save the design.



Next click on button to build the design. After it's done, export the hardware for SDK use. Make sure you export the generated bitstream as well.



4. Create a Hardware Project in Xilinx SDK


Create a new Hardware Platform Specification project as shown below.image


Click on Browse.. button to choose the exported hardware files from Xilinx Vivado.



Choose the exported .hdf file located under a folder with extension name .sdk




5. Create a BSP Project in Xilinx SDK


Create a new BSP project as shown below.



Choose the hardware project you created in the previous step as the Hardware Platform. Choose psu_cortexr5_0 as the CPU type. Choose freertos10_xilinx as BSP OS.




6. Create an Application Project in Xilinx SDK


Create an application project as shown below.



Select freertos10_xilinx as the OS Platform. Choose the hardware project name you created before as the Hardware Platform. Select psu_cortexr5_0 as the Processor.



Xilinx SDK will automatically create dependency among your application, BSP and hardware projects so you don't need to explicitly create it.



7. Modify Source Code and Build Application


Go to the source folder of the application project, remove .c file and copy CAN_example.c file attached to this review into the source folder.

Click on button to build the application.image



8. Run the Application


Connect power to Ultra96 board and press the power switch SW3 close to the power jack.

Click on button to program FPGA. Then launch the application by right clicking on the application project and click on Launch on Hardware menu item as shown below.




8. Example Results


CAN traffic from Ultra96's view. It shows Ultra96 first receives a CAN message (CAN ID 0x7D1) then it sends out a CAN message (CAN ID 0x7D0). Both messages have the same 8-byte payload data.



The above screen shot can be verified from CAN tool VN1630A's view. It shows VN1630A sends out 0x7D1 message first then it receives 0x7D0 message. It sends 0x7D1 message every 100ms. No CAN bus error is observed.





Part II - Road Sign Image Classification Example



As mentioned before, this example is a demo of the result of a Xilinx wiki article - Zynq UltraScale+ MPSoC Accelerated Image Classification via Binary Neural Network TechTip. My set up for this demo is as following:


- Avnet Ultra96 Dev Board

- Samsung HD TV with VGA port

- Mini DisplayPort to VGA Video Adapter Converter

- Logitech C922 Pro Stream Webcam

- Dell USB Mouse

- HP BT Keyboard


Since the wiki article is very detailed about the steps running the demo, I won't repeat them in this review. If you want to run the demo by yourself, please read the article carefully. Especially don't forget to copy the boot files under ultra96 folder to the root folder. Also the newer version demo (i.e., 20180814_zcu102_ultra96_aicdemo_20181.zip) didn't work for me. It stalled at the following screen forever. The old version 20180424_zcu102_ultra96_aicdemo.img

worked fine.



First, I tried the software image classification (without hardware acceleration) on the image library stored on SD card. It was very slow and didn't seem moving forward at all.



Next, I tried the HW acceleration version and it classified the library images dramatically faster. Each image might take less than a second to classify it.


I printed out a few road signs and did a live test on these printed images.



A few things have been observed from the live test:

1. The road sign too close or too far from the webcam won't be recognized

2. Only one road sign can be recognized even the webcam captured multiple road signs

3. Upside down signs can be recognized, but 90 degree rotation make them not recognized

I think with more supervised training, the neural network model could be improved.



Overall, the performance difference between HW & SW image classification is so huge and I am very impressive by the HW acceleration. I think before the dedicated ASIC chips become widely available, Zynq UltraScale+ MPSoC could be a good candidate platform for autonomous driving development.





Ultra96 dev board is a very competitive low cost development system for engineers, makers and hobbyists to get hands-on experiences on the powerful Zynq UltraScale+ devices. It can also be used as a fast prototype for many application such as deep learning on edge nodes. I am really impressed by its high performance to price ratio.