Digilent Zybo Z7 + Pcam 5C - Review

Table of contents

RoadTest: Digilent Zybo Z7 + Pcam 5C

Author: fyaocn

Creation date:

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: No

What were the biggest problems encountered?: So far, it is perfect.

Detailed Review:


I have not expect this roadtest being such a difficult one, furthermore exciting one as well. I have to score 60 since that is the max score available.

Even take a lot time on such large DevPack installation again and again, the result is beyond expectation. Since version 2019.1, webpack selection offer full function with further upgrade to more pro choice.


1.Zybo Z7

The Zybo Z7 is a feature-rich, ready-to-use embedded software and digital circuit development board built around the Xilinx Zynq-7000 family. The Programmable System-on-Chip (AP SoC) architecture integrates a dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic.

The Zybo Z7's video-capable feature set includes a MIPI CSI-2 compatible Pcam connector, HDMI input, HDMI output, and high DDR3L bandwidth.

The imaging module  Pcam 5C, with a factory-installed M12 fixed focus lens, is designed around the Omnivision OV5640 5 megapixel (MP) color image sensor. Data is transferred over a dual-lane MIPI CSI-2 interface supporting video streaming formats up to 1080p (at 30 frames per second) and 720p (at 60 frames per second).

2. General Idea of the Roadtest

Unlike normal roadtest I joint before, this roadtest on Zybo Z7 is around my ongoing project of TennisBot, which can find tennis automatically with AI vision abilities. This would be good for pro-camera with IP cores for sensor interfacing, real-time image processing pipeline and video outputs, with room for user differentiation.The tennisbot shall use camera to catch picture, and analysis the Tennis image in the Picture. Then control the wheels to move near the tennis, catch the one within the view.The high performance of FPGA can make the action of BOT fast and efficiency.

Besides routine test procedure, this roadtest shall be focus on features of cameras and high speed connectivity from the latest 4K and 8K sensors with a fully flexible image and video processing pipeline. With reference to https://www.xilinx.com/applications/broadcast/cameras.html


3. Unboxing and  Hardware Study, IDE Installation

3.1 Unboxing

Here is what inside the box, and Powerful inside.


3.2 Vivado HLX Installation

Installation takes me a lot time. From version 2018,3 to 2019.1, the web

After installation, the board init script in Vivado_init.tcl shall be edited and copied to User space.

Then sdk for the board shall be installed afterward. But with web installation that is much simple, only time is too long for most people,

Board installation require vivado_init.tcl in right location as,

Only then can you find the board,




4. Demo project


4.1 Create new project Blinky, with board zybo selected.


Then add constrains from imported XDC files,

Then create source file Blinky.v in Verilog Code Type,


Edit the program and insert the user verilog code,

`timescale 1ns / 1ps

module blinky(
    input clk,
    output led
    reg [24:0] count = 0;

assign led = count[24];

always @ (posedge(clk)) count <= count + 1;



Now, start the Program Flow, first one, run RTL analysis,

Then Run Synthesis

Run Implementation,

Generate Bitstream

Open Hardware manager

Program the Device,

4.2 Create LED project wit Vivado IP Integrator

Create the project


Then Create IP Integrator

Create Block design, connect component with bottons and LEDs


ADD IP with zybo board

Run block automation and connection Automation


Validate the design, there are warnings, check in the message pane and fix it automatically. Try agian until it is sucessful.



Create HDL wrapper,

Generate Bitstream,

Export Hardware,

The final step is put Bitstream together and Export Hardware, This action shall invoke Xilinux SDK

That is it,

Development in SDK is the same as what you have done in Eclipse GCC,

Creating new project and coding,

here is code for main.c

//AXI GPIO driver
#include "xgpio.h"

//send data over UART
#include "xil_printf.h"

//information about AXI peripherals
#include "xparameters.h"

int main()
XGpio gpio;
u32 btn, led;

XGpio_Initialize(&gpio, 0);

XGpio_SetDataDirection(&gpio, 2, 0x00000000); // set LED GPIO channel tristates to All Output
XGpio_SetDataDirection(&gpio, 1, 0xFFFFFFFF); // set BTN GPIO channel tristates to All Input

while (1)
btn = XGpio_DiscreteRead(&gpio, 1);

if (btn != 0) // turn all LEDs on when any button is pressed
led = 0xFFFFFFFF;
led = 0x00000000;

XGpio_DiscreteWrite(&gpio, 2, led);

xil_printf("\rbutton state: %08x", btn);

Final step, program FPGA

Open Serial Terminal in local host computer , such as PUTTY

Here is what return in host computer. The bit rate is incompatible, but the flashing text mean it works.


5. Camera image pipeline and process the image stream ,

This is too long a blog and too many screenshots.

In fact, I have tried my best to use the minimum of picture, there could be more. Since the xiLinux FPGA program flow is so CONCISE, not complicate. The whole IDE has been as User-Friendly as it should be.

To image you have build one fully Personal Configurated Digital Processor in serveral hours, that is what this Zybo dev-board brings about.

What bothers developers is not this IDE tools, but the understanding to the computer Architecture and Communication Protocle. There have been as many as IP provided by Vivado 2019.1, I think it worth the cost.


With regards to  the  planned roadtest to camera image pipeline and process the image stream with AI models . That would be more challenging and of course , more exciting.

But I have tryed for 4 weeks to make little progress. I have import the demo project Zybo-Z7-20-pcam-5c.


But this is for zybo-z7-20 and Vivado 2016.04 is required. I have to uninstall Vivado 2019.1 and reinstall webpack 2016.4. This have been many error reported and fixed one by one. Unlike the Quartus 18.1 I used before, Vivado shows more component and settings, it appears not to be got within one month. The learning curve is fairly steep. I have wrongly erase the ex-factory firmware which is demo for PCAM, assumed that I can reprogram the bitstream file agian easily. I shall post the another blog on how to solve the problems later.


While. there are some progress, import the zybo-z7-pcam project by running source ./create-project.tcl in TCL concole,

Here is  the full imported design ang building process

With some parameters ajustment , I can build the final bitstream file. But the mail clock report wrong and can not programed into the flash. That part is about Programming skill and not the problems with the Vivado or Hardware.

Another plan on running AI-module in FPGA, there have been many essay and opensource model like object-detection in verilog.

Here is the implement design of pcam, the camera feed image into the system and output HDMI

The system shall process the image and feed back the center of detected object within view, then control motors with PWM IP Block. The resources is still available for more functions


To sum up, this is really multifunction Dev Tools to unlash the imagination. With all the difficult, I still think the toolset is eay to use with clear instruction and tips. This is a software package of several Gigabyte, there is no reason for quick jumpstart.