Table of contents

RoadTest: USB104 A7: Artix-7 FPGA Development Board

Author: dimiterk

Creation date: 4 Jan 2021

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: USB104A7 has the same FPGA as ARTY A7-100T also from Digilent but with less pins and no Ethernet.

What were the biggest problems encountered?: Lack of ZMOD selection means you have to design your own at the moment. Increased complexity due to requirements of ZMOD MCU.

Detailed Review:

This roadtest will take a look at the USB104-A7 Artix 7 FPGA board from Digilent. Many thanks to Element 14 (Randall Scasny rscasny and Digilent for providing the hardware for this review.

1. Quick introduction

The USB104 A7 comes with an Artix 7 series FPGA from Xilinx.  As one can deduce from the naming, this board comes in a PC/104 form factor.

However instead of the venerable 40 pin 0.1 inch connector , the stack-ability is offloaded to a ZMOD connector placed right at the center of the board

USB104A7 comes with 3 PMODS , a USB connection and emebdded JTAG functionality.

Digilent has done a good job providing descriptions for each of the hardware blocks as seen here:

https://reference.digilentinc.com/reference/programmable-logic/usb104a7/start

The dev-board sports an industrial temperature range Artix  XC7A100T-1CSG324I  FPGA which comes in a speed grade -1.  This is a cost optimized version of the higher speed varieties -2 and -3.

For this road-test I planned to do 3 things:

a) Run the OOB design package examples

b) Implement a simple video processing application on USB104A7

c) Port Linux to the USB104A7 board

First some unpacking photos:

I

The board comes with a wall wart with both a European and a North American plug.  In addition , there is a USB Type A cable.

No ZMODs were provided with the package so I could not test one of the reference designs which tested the DSPI interface using a ADC ZMOD.

The board also contains a USB hub which connects both the FTDI chipset with a parallel interface to the FPGA . This is used for data transfer between PC and USB104A7. This is helpful for entry level HIL (Hardware in the loop) designs due to the low bandwidth. However the lack of a Python interface requires using the Adept software framework.

The initial idea was to interface with a SPI ADC using a PMOD however I wanted to explore the breadth of the  board even more so I tried to implement Linux and run the ADC driver from the userspace. This was only part done since while the Linux image works on QEMU emulator it does not run on the board at the moment.

2. Out of Box designs

The board comes with two example apps.

Blinky

The board comes pre-loaded with a blinky app stored on the SPI flash. Pressing the button shows a message on the UART terminal.

DSPI

This design example showcases the parallel data transfer between the FPGA and USB port using the FT232H IC. However the hub can only support USB2.0 speeds. This FW makes use of the ZMODs.

The OOB design configured the Microblaze as a MCU without a MMU unit. One other thing I noticed is that the default design for the qspi configures it without support for the primitives.

The other issue once can point out is that the MIG is fed directly from the clock pin. Using a clocking wizard and providing the MIG vwith clocks from it gives some weird clock violations.

as seen here:

https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/CLOCK-DEDICATED-ROUTE-set-to-BACKBONE/td-p/741004

https://forums.xilinx.com/t5/Implementation/Vivado-DDR3-mig-error-Sub-optimal-placement-for-a-clock-capable/td-p/448644

3. Video application

Here we'll create a system with MicroBlaze and the MIG. Instead of an image sensor will use the TPG which will write to DDR Memory through the MIG.

A PMOD VGA was used to interface the board to a VGA monitor. The same design can be easily adapted if one is using a HDMI ZMOD.

The first step was to modify the OOB design by adding the following blocks:

a) Test pattern generator

b) timing controller

c) AXI in to Video out

d) clocking wizard

e) VDMA

TPG

The TPG was configured for 640x480 resolution.

VTC

The video timing controller was configured for 640x480 resolution. A note here; If you are using the VTC with newer Vivado /Vitis versions you may have to enter the timing data manually.

AXI stream to Video out

The AXI stream to Video out was configured in slave mode.

Clocking Wizard

The design is configured so that the clocking wizard it is clocked with a 100Mhz clock from the MIG. The clocking wizard generates a VGA 25.2Mhz clock.

All the AXI peripherals including the MIG are clocked with the same 100Mhz clock from ui_clk. So basically there are only 3 clock domains 200Mhz, 100Mhz, and 25.2 Mhz.

VDMA

Configuring the DDR3 MIG.

The first design example simply piped the TPG data to a VGA screen.

The second design was augmented with a VDMA , in order to write and read the incoming data to DDR3 memory.

The second design example augments the initial design with a VDMA. The VDMA is configured using 3 frames for 640x480 resolution using a 24bit AXI stream width.

The design example on the Github repo shows how to exercise the TPG to write various patterns on the monitor.

4. Porting Linux

To make the device capable of running Linux the Microbalze has to be modified with an MMU.

In addition a timer needs to be added.

After recompiling, the design xpm is exported.  The next step was using Vitis 2020.1 to export the design from the xsa generated by Vivado. Petalinux was then used to produce a linux image.

Before exporting the image I tested the DDR.

One issue is that Vitis 2020.1 has some changes from the 2019.1 SDK so I had to use the xsct command line for programming.

I tested the image on Qemu , however burning the image on the SPI NOR flash failed to work since the image is larger than QSPI. This will require taking another look at the QSPI memeory map to see how to make the lInux image fit.

AXI TFT display + text

The last thing I tried for this project was to use the AXI TFT IP. This module is useful when you want to write data to the screen via the memory mapped AXI bus. Here's I used the example provided to write a string to the screen and plot two lines.

In the past versions of Vivado there were a couple of ways to enable writing custom text on the VGA monitor. However Xilinx has started deprecating perfectly working IPs lately.

The On Screen Display (OSD) IP is one example that has been retired by Xilinx which at the moment recommends using the video mixer IP with custom code in order to write text on screen.

Another issue I found was that the latest version of Vitis removes the presets from the timing controller which requires one to manually enter the timing parameters.

Code for the designs is given on the Github repo as always:

https://github.com/Q-point/Microblaze-USB104A7_Video

Some further ideas for projects are:

a) Run a RISC-V CPU on the USB104A7 instead of Microblaze

b) Build a HDMI ZMOD for image processing

c) Test NVDLA accelerator with Microblaze

Wishlist:

I would have preferred that this board had Ethernet as opposed to simple serial and USB2.0 connectivity

Also a USB 3 PHY would have been helpful. One could use the board for SDR applications that require large data transfers.

A USB C connector would have given the board that present vibe. Multiplexing both JTAG and DSPI (FTDI) on single USB PHY looks like a recipe for decreased bandwidth

5. Verdict

The good:

1. USB104 A7 comes in a compact PC/104 form factor.

2. DDR voltage operation can be configured via a switch

3. Embedded Digilent JTAG programmer

4. Industrial temp grade device.

The bad:

1. Low speed grade device for main FPGA makes timing closure difficult

2. Only 16MB of NOR flash which means little space for an embedded Linux solution.

3. USB Type A connector, no USB C

4. No Ethernet so you'll need a PMOD external PHY.