Group Actions
Engagement
  • Author Author: jc2048
  • Date Created: Date Created
  • Views 7822 views
  • Likes 10 likes
  • Comments 21 comments
Related
Recommended

555 Voltage Controlled Oscillator

jc2048
555 Voltage Controlled Oscillator

In the last blog, I used a 555 timer to make a simple oscillator. It used an
additional transistor, as a current source for the capacitor charging, in place
of the resistor that would usually be used. Although the blog focused on the
linear nature of the ramp and the resulting sawtooth waveform, my real interest
was slightly different as I wanted to use it as a VCO (Voltage Controlled
Oscillator).

Here I'm taking that circuit and adapting it so that I can control the current.
I need the control input to accept voltages in the range of 0-3.3V and to be a
very high impedance as it will be controlled by the voltage across a capacitor
(hopefully without discharging it). This is the circuit I ended up with.
image
On the right we still have the transistor and emitter resistor that function as
a current source, but now, instead of the base voltage being fixed by a
potential divider, it can be adjusted by the op amp. To the left, I have a
mirror image of the transistor and emitter resistor. Although the transistors
won't match exactly, the currents in the two 620 resistors will be approximately
the same. The current in the left 620 flows down through the transistor and
mostly out of the collector where it develops a voltage across the 3k3 resistor
that can be read by the op amp. That then gives voltage feedback that's
equivalent to the current that's flowing down into the capacitor. Final step is
for the op amp to compare that with the control voltage going in and drive the
bases in such a way that the two match. Op amps are good at that kind of thing,
particularly when you get the two inputs the right way round! (Yes, initially I
managed to overlook the inversion in the feedback path given by the transistor.)

It's not the most inspired piece of design ever and you probably wouldn't want
to use it for instrumentation (V -> f converter), but for what I want it will
suffice, though there is one snag with it which I will need to work around.

Here's a graph of the resulting frequency for different control voltages.
image
It's fairly linear, though there's a slight offset (it doesn't look like it
passes through the origin: thinking back, it's possible I had a 'scope probe on
the timing capacitor stealing some of the current, though a bipolar 555 will be
biasing it a little as well). The range is also somewhat limited. At the lower
end it becomes increasingly jittery when the frequency gets down to a few
hundred Hertz, presumably because of the low currents involved, so maybe two
decades at best without some more work.

If I tell you what the snag is - the oscillator stops with a control voltage of
0V, meaning there will no longer be edges in the output waveform - you may be
able to guess where I'm going for part three.

Next blog: 555 Phase-Locked Loop (PLL)

If you found this interesting and would like to see more blogs I've written, a
list can be found here: jc2048 blog index

References
[1] https://www.st.com/en/clocks-and-timers/ne555.html
[2] https://www.ti.com/lit/ds/symlink/ne555.pdf

Parents

  • Nice! I would not have guessed it would become a VCO, and that's a great range, more than 10:1. 

    I can guess fairly well (I think) where you are going with this, because I had a similarish need myself a while back, although I didn't blog about it because I didn't get to any decent point, my VHDL knowledge is really poor. My VHDL implementation did something, but there were enough grey areas in my understanding that I couldn't feel confident in what I was implementing was what I intended.

    In my case it was for a radio project, and eventually I used a ready-made clock synth chip, which still irritates me, because I really wanted to get it working with a homemade PLL.

  • in reply to shabaz

    I wouldn't know where to start with the phase comparator from scratch, but I came across an application brief in an old Xilinx databook (it shows it in schematic form), so I'm going to try that. I've also found an ST datasheet that, while it doesn't give a circuit, does give a state transition diagram, so I might try that too. (It's quite possible they're both the same thing.)

    If it works, maybe I could then try for a LW receiver. (The 555 isn't really fast enough for MW if you need 4x the carrier to get the quadrature waveforms.)

  • in reply to jc2048

    Progress update (just in case anyone is interested).

    image

    That's the best I've managed so far - that's with a Max II CPLD doing the logic bit. Yellow is a 10kHz reference signal divided down from a xtal osc. Blue is the 555 VCO output that's supposed to be locking to it. It is locked, but in a 3:4 ratio (fractional locking!). The reason seems to be because Quartus is helpfully 'elaborating' my design for me and I can't seem to stop it (the phase comparator design is an asynchronous state machine, so it needs to be implemented as designed). I might give up with fiddling with all the myriad of settings and try it later with a Lattice part.

  • in reply to jc2048

    Hi Jon,

    Good results, neat idea using the CPLD to get around the FPGA implementation. I think a separate phase comparator could be easier, since as you say even the CPLD portion implementation will be different. I remember you ordered some 74HC4046, the phase comparator portion of that could be used. From memory it may be good for several MHz. 

  • in reply to jc2048

    Sorry just saw this message now : ( 

    Zero e-mails and no notification, despite your comment being a direct reply to me.

    I guess a non-SDR style receiver could be possible, since that won't need the 4x carrier, or alternatively an LC circuit could be used for the desired frequency. There's a nice method described in this PDF, http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.399.7115&rep=rep1&type=pdf

    (no way to type a proper hyperlink in this editor either : (

    in diagram 5(b). 

  • in reply to shabaz

    Thanks for the comments.

    The Max II part is essentially a simple FPGA, even though they call it a CPLD. It's got the usual FPGA structure of a LUT and flip-flop in a cell. I just used it because it's a simple little board to work with and wasn't being used for anything else.

    I don't know for sure that the problem lies with the synthesis and fitting - the design is working with edges and the plug-in breadboard is pretty messy, given the fast edges the CPLD is capable of - but the RTL view after the fitter seems different to what comes out of the synthesis (which does match the circuit I describe with the VHDL). Anyway, the simplest thing to do is to move to a completely different set-up and see what, if anything, changes.

    If I eventually get to something that works, I'll write it up as a blog and then go on a do a simple frequency synthesizer with it, as that seems like the natural next step.

    One of the phase comparators in the HC4046 is functionally the same as what I'm trying to implement, but it feels like cheating to use that rather than roll my own. Now I've started, I want to get this working. It's something interesting that I've not done before.

    BTW I shouldn't really use the term 'locking', as it stands at  the moment, because it wouldn't track properly if the reference frequency was slowly changed. The loop is solving a problem, but it's the wrong problem it's solving.

Comment
  • in reply to shabaz

    Thanks for the comments.

    The Max II part is essentially a simple FPGA, even though they call it a CPLD. It's got the usual FPGA structure of a LUT and flip-flop in a cell. I just used it because it's a simple little board to work with and wasn't being used for anything else.

    I don't know for sure that the problem lies with the synthesis and fitting - the design is working with edges and the plug-in breadboard is pretty messy, given the fast edges the CPLD is capable of - but the RTL view after the fitter seems different to what comes out of the synthesis (which does match the circuit I describe with the VHDL). Anyway, the simplest thing to do is to move to a completely different set-up and see what, if anything, changes.

    If I eventually get to something that works, I'll write it up as a blog and then go on a do a simple frequency synthesizer with it, as that seems like the natural next step.

    One of the phase comparators in the HC4046 is functionally the same as what I'm trying to implement, but it feels like cheating to use that rather than roll my own. Now I've started, I want to get this working. It's something interesting that I've not done before.

    BTW I shouldn't really use the term 'locking', as it stands at  the moment, because it wouldn't track properly if the reference frequency was slowly changed. The loop is solving a problem, but it's the wrong problem it's solving.

Children
  • in reply to jc2048

    Same VHDL design seems fine with my Brevia 2 board (XP2 FPGA with Diamond 3.12 IDE). Here's the 555 ramp waveform locked to 10kHz divided down from the board oscillator.

    image
    Lots of jitter, though. I wasn't very scientific with the loop filter (just picked up some likely looking bits from the bench), so I ought to be able to improve that.

    image
    It was really nice seeing the 555 waveform snap into place the moment the programming of the FPGA had completed.

  • in reply to jc2048

    Hi Jon,

    That's really neat. I've never seen a PLL possible with sawtooth. 

    It could be possible to make a really high-end analog synth : ) A bank of 555's, connected to the FPGA : )

  • in reply to jc2048

    "Same VHDL design seems fine with my Brevia 2 board"

    Is that because it kept your design after Syntheseis and Implement, while the Quartus chain didn't?

  • in reply to Jan Cumps

    Lattice warns about the combinatorial loops, because it thinks I've got the design wrong (wrongly implied memory, rather than this being very deliberate memory), but it synthesizes it as written, and the placement and fitting leaves it intact. (I haven't necessarily got default settings for everything, though - it all gets messy because there are tool settings, a constraints file for the design, and it's possible to put stuff in the HDL, some of which applies to the synthesis and some which also gets passed on to the placement and fittting).

    I would guess Quartus is being too agressive with optimising it, but I'm not 100% sure, and it's possible I did something else wrong. Now that I know that the code is ok and the design works as it should, I could go back and see if I can get it to work with Quartus.

  • in reply to shabaz

    I don't know if 'high-end' is really the right phrase, but yes, you could do something like that. I don't think you could get it to lock fast enough to play music with a single circuit, but a bank of them, a bit like they used to do with electronic organs with divider chains could be quite quite interesting. The capacitor voltage would need a high-impedance buffer so as not to load it too much. The jitter would need improving, though.

    When I've got some time, I'll blog this, and then anyone who wants to can experiment with the phase comparator. For most (low-frequency) purposes, you'd be better off with a 4046, but it's quite educational building your own.

    This phase comparator, that I got from an old 1989(!) Xilinx databook, is the same as one of those in the HC4046 (ST give a state transition diagram that's equivalent to the circuit). My guess is that it's a known circuit that goes back to the year dot and it probably crops up all over the place. I don't have any of the classic books on PLLs, but presumably they take you through all this kind of stuff.