555 Phase-Locked Loop (PLL)

RE: 555 Phase-Locked Loop (PLL)

michaelkellett — Fri, 01 Jul 2022 14:24:58 GMT

Really good blog - thanks.

I have my Efinix board and hope to play with the software tomorrow. I may well give this a try.

RE: 555 Phase-Locked Loop (PLL)

jc2048 — Thu, 30 Jun 2022 14:43:20 GMT

In The Designer's Guide to VHDL (2nd edition, 2002), Ashenden says "Occasionally we might design an asynchronous circuit: a sequential circuit without a clock or enable input. Such circuits store state using combinatorial feedback loops. The synthesis standard and most synthesis tools do not support synthesis of these kinds of circuits."

RE: 555 Phase-Locked Loop (PLL)

Jan Cumps — Thu, 30 Jun 2022 11:53:37 GMT

[mention:4f57fc9d538949ad9eb336ddb9469bb8:e9ed411860ed4f2ba0265705b8793d05], there's an extra space in the url to your summary page. It navigates to an error page.

RE: 555 Phase-Locked Loop (PLL)

shabaz — Wed, 29 Jun 2022 22:38:53 GMT

I'm wondering whether I should try to resurrect the PLL HDL which I was working on, in case I can get it going. It would be awesome to integrate the phase comparator HDL which you've created, since my HDL was missing that (I was planning to use an external one).

I too was using Lattice, and was wondering, have you found any way of viewing the top-level graphically with IceCube2? I've searched online, and can't see how to do it. After there are more than a few components in the top level, it gets tricky (to me at least) to mentally picture how they all connect, and I probably sketched a diagram at the time on paper, but I've lost it, so was wondering if there was a way to auto-generate a diagram.

RE: 555 Phase-Locked Loop (PLL)

robogary — Wed, 29 Jun 2022 20:26:13 GMT

wow !

RE: 555 Phase-Locked Loop (PLL)

genebren — Wed, 29 Jun 2022 16:12:10 GMT

Very interesting blog topic and implementation. I look forward to your further developments on this topic.

RE: 555 Phase-Locked Loop (PLL)

cstanton — Wed, 29 Jun 2022 12:28:44 GMT

Cleaned it up for you:

RE: 555 Phase-Locked Loop (PLL)

shabaz — Wed, 29 Jun 2022 11:19:55 GMT

Hi Jon,

Thanks for writing this up, and providing the VHDL. It makes it all a lot clearer, and I doubt there are many other resources showing in this level of practical detail how a PLL can be implemented using an FPGA.