MPC5746M: Qorivva multi-core 32-bit MCU for Powertrain Applications [New]*

autoembedded — Fri, 08 Oct 2021 04:51:57 GMT

Current Revision posted to Documents by autoembedded on 10/8/2021 4:51:57 AM

The Qorivva MPC5746M Power Architecture® MCU is Freescale's first powertrain device supporting more than two processing cores and peripherals to meet next-generation advanced engine control, functional safety and security requirements.

The MPC5746M is part of the SafeAssure program, which is designed to help system manufacturers achieve compliance with functional safety standards such as ISO 26262 for ASIL-D safety integrity.

In order to minimize additional software and module level features to reach this target, on-chip redundancy is offered for the critical components of the microcontroller (multiple CPU computational cores with delayed lockstep, I/O processor core, DMA controller, interrupt controller, dual crossbar bus system, memory protection unit, fault collection unit, flash memory and RAM controllers, peripheral bus bridge, system and watchdog timers and end to end ECC).

Main Features:

Two independent e200z4 cores operating up to 200 MHz

- Single 200 MHz e200z4 core for delayed lockstep

- Single e200z4 I/O core operating up to 200 MHz

On-chip DSP and floating point unit
Built to support functional safety (ISO 26262 / ASIL-D)
120-channel general timer module (GTM103)
Up to 64-channel eDMA
Up to 60-channel analog-to-digital converters (ADC)

- Includes 6 x ΣΔ ADC converters

Go to MPC5746M Homepage to learn more.

Tags: 32bit, freescaledocs, freescale, power_architecture, qorivva, automotive, mcu, powertrain, auto, innovation, safeassure