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Tang Nano 9k: Using Internal PSRAM in Gowin FPGAs

shabaz — Thu, 08 Oct 2026 20:58:23 GMT

Table of Contents Introduction PSRAM Overview Adding Gowin IP VHDL Walk-Through Entity: Ports to the Outside World PLL Component PSRAM Component Process: Asynchronous Reset Function Process: Registered Portion Read Operation Underway Calibra...(read more)

Tang Nano Series and Gowin FPGAs for Beginners: A Practical Guide, Part 1

shabaz — Mon, 05 Oct 2026 03:48:35 GMT

Table of Contents Introduction Microcontroller vs FPGA: Pros and Cons What’s Inside the FPGAs? Memory and Flash FPGA Comparison Tang Nano Board Differences Tang Nano Pinouts Tang Nano 1k Pinout Tang Nano 9k Pinout Tang Nano 20k Pinout D...(read more)

High Speed Fiber Optic Data Transmission

ad0es — Sat, 03 Oct 2026 20:28:35 GMT

Recent additions Chapter II Small board for single/dual ADC. (read more)

Bringing up an AD9361-class 2T2R transceiver on Zynq-7000: Part 1 – clock plan, data interface, and the first link

LeslieGuo — Sun, 20 Sep 2026 06:42:11 GMT

I'm starting a project log for a wideband 2T2R RF front end built around an AD9361-class transceiver paired with a Zynq-7000 (the same class of platform many SDR boards use). The goal is a working, documented bring-up: stable clocking, a reliable...(read more)

Hardware Accelerator for Hyperspectral Image Processing

afernandez — Tue, 14 Jul 2026 07:12:39 GMT

Hi, community! I’m writing this post because I’d like to share one of the projects I have been working on, a hardware accelerator written in SystemVerilog for processing hyperspectral image vectors. First of all, I want to give some cont...(read more)

Lattice iCE40UP5K-EVB Evaluation Board - Part 2: Using the DSP Multiplier

jc2048 — Mon, 30 Mar 2026 11:02:16 GMT

Introduction This is a follow-on from this blog and will make more sense if you read that one first. The hardware is exactly the same as in that previous blog, all I'm going to do with this one is adapt (hack might be a better word) the VHDL to perfo...(read more)

Lattice iCE40UP5K-EVB Evaluation Board Outputing Audio Sine Waves Over an Optical S/PDIF Interface

jc2048 — Fri, 20 Mar 2026 08:17:38 GMT

Introduction Quite a long way back, I was fortunate enough to win a shopping basket in a Project 14 competition and the main item I purchased with it was an evaluation board for a Lattice iCE40UP5K FPGA device. Here, finally, is an informal look at t...(read more)

Fast VHDL CORDIC Sine and Cosine Component on Lattice XP2 Device Using Diamond 3.12 Part 2

jc2048 — Mon, 16 Feb 2026 22:02:29 GMT

Introduction This is a follow-up to Fast VHDL CORDIC Sine and Cosine Component on Lattice XP2 Device Using Diamond 3.12 I thought I had actually used the CORDIC component for real, but I was getting confused with other blogs, so now I'm going t...(read more)

The Art of FPGA Design Season 2 Post 29

fpgaguru — Wed, 27 Aug 2025 18:51:12 GMT

Can IIR FIlters Be Fully Pipelined? We have reached the final post in this series on LWDF IIR filters. I hope that I was able to convince you that many, if not all, of the perceived disadvantages of IIR filters can be addressed while maintaining thei...(read more)

The Art of FPGA Design Season 2 Post 28

fpgaguru — Tue, 19 Aug 2025 22:39:56 GMT

Look Ma, no multipliers! The last LWDF IIR filter example I gave was unusual in the sense that it was multiplierless, all the coefficients were powers of two, which in FPGA hardware cost absolutely nothing. Of course, this restricts considerably the ...(read more)

The Art of FPGA Design Season 2 Post 27

fpgaguru — Mon, 18 Aug 2025 02:12:51 GMT

Linear Phase IIR Filters? Part 3 Finally, the third and probably most efficient, but also least known and used way to achieve near linear phase IIR filters is the object of this post. Absolute linear phase, or equivalently constant group delay,...(read more)

The Art of FPGA Design Season 2 Post 26

fpgaguru — Mon, 11 Aug 2025 01:11:11 GMT

Linear Phase IIR Filters? Part 2 The forward-backward method of turning any non-linear phase IIR into a "linear phase" one at a much lower hardware cost than the classic linear phase FIR implementation I showed in the previous blog post wor...(read more)

The Art of FPGA Design Season 2 Post 25

fpgaguru — Sat, 09 Aug 2025 19:13:22 GMT

Linear Phase IIR Filters? Part 1 I hope everybody can agree by now that IIR filters, especially in their LWDF form, are at least interesting and worth a look. I mean, an order of magnitude on average less resources compared with an equivalent FIR has...(read more)

The Art of FPGA Design Season 2 Post 24

fpgaguru — Fri, 08 Aug 2025 22:11:13 GMT

LWDF IIR Filter Design Examples If you made it this far through the math wilderness, congratulations, it's time now to put all that knowledge to good use and design some LWDF IIR filters. I will start with some simple ones first, graduating then ...(read more)

The Art of FPGA Design Season 2 Post 23

fpgaguru — Thu, 07 Aug 2025 02:10:57 GMT

Implementing the First and Second Order All Pass Sections with DSP Primitives We are almost there now. We have the LWDF IIR filter architecture, which is much better then the classic biquad cascade: It is made out of two parallel all pass path...(read more)