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Lattice iCE40UP5K-EVB Evaluation Board - Part 2: Using the DSP Multiplier

jc2048 — Mon, 30 Mar 2026 11:02:16 GMT

Introduction This is a follow-on from this blog and will make more sense if you read that one first. The hardware is exactly the same as in that previous blog, all I'm going to do with this one is adapt (hack might be a better word) the VHDL to perfo...(read more)

Lattice iCE40UP5K-EVB Evaluation Board Outputing Audio Sine Waves Over an Optical S/PDIF Interface

jc2048 — Fri, 20 Mar 2026 08:17:38 GMT

Introduction Quite a long way back, I was fortunate enough to win a shopping basket in a Project 14 competition and the main item I purchased with it was an evaluation board for a Lattice iCE40UP5K FPGA device. Here, finally, is an informal look at t...(read more)

Fast VHDL CORDIC Sine and Cosine Component on Lattice XP2 Device Using Diamond 3.12 Part 2

jc2048 — Mon, 16 Feb 2026 22:02:29 GMT

Introduction This is a follow-up to Fast VHDL CORDIC Sine and Cosine Component on Lattice XP2 Device Using Diamond 3.12 I thought I had actually used the CORDIC component for real, but I was getting confused with other blogs, so now I'm going t...(read more)

The Art of FPGA Design Season 2 Post 29

fpgaguru — Wed, 27 Aug 2025 18:51:12 GMT

Can IIR FIlters Be Fully Pipelined? We have reached the final post in this series on LWDF IIR filters. I hope that I was able to convince you that many, if not all, of the perceived disadvantages of IIR filters can be addressed while maintaining thei...(read more)

The Art of FPGA Design Season 2 Post 28

fpgaguru — Tue, 19 Aug 2025 22:39:56 GMT

Look Ma, no multipliers! The last LWDF IIR filter example I gave was unusual in the sense that it was multiplierless, all the coefficients were powers of two, which in FPGA hardware cost absolutely nothing. Of course, this restricts considerably the ...(read more)

The Art of FPGA Design Season 2 Post 27

fpgaguru — Mon, 18 Aug 2025 02:12:51 GMT

Linear Phase IIR Filters? Part 3 Finally, the third and probably most efficient, but also least known and used way to achieve near linear phase IIR filters is the object of this post. Absolute linear phase, or equivalently constant group delay,...(read more)

The Art of FPGA Design Season 2 Post 26

fpgaguru — Mon, 11 Aug 2025 01:11:11 GMT

Linear Phase IIR Filters? Part 2 The forward-backward method of turning any non-linear phase IIR into a "linear phase" one at a much lower hardware cost than the classic linear phase FIR implementation I showed in the previous blog post wor...(read more)

The Art of FPGA Design Season 2 Post 25

fpgaguru — Sat, 09 Aug 2025 19:13:22 GMT

Linear Phase IIR Filters? Part 1 I hope everybody can agree by now that IIR filters, especially in their LWDF form, are at least interesting and worth a look. I mean, an order of magnitude on average less resources compared with an equivalent FIR has...(read more)

The Art of FPGA Design Season 2 Post 24

fpgaguru — Fri, 08 Aug 2025 22:11:13 GMT

LWDF IIR Filter Design Examples If you made it this far through the math wilderness, congratulations, it's time now to put all that knowledge to good use and design some LWDF IIR filters. I will start with some simple ones first, graduating then ...(read more)

The Art of FPGA Design Season 2 Post 23

fpgaguru — Thu, 07 Aug 2025 02:10:57 GMT

Implementing the First and Second Order All Pass Sections with DSP Primitives We are almost there now. We have the LWDF IIR filter architecture, which is much better then the classic biquad cascade: It is made out of two parallel all pass path...(read more)

The Art of FPGA Design Season 2 Post 22

fpgaguru — Wed, 06 Aug 2025 19:52:26 GMT

LWDF IIRs I am finally ready now to discuss the LWDF IIR filter architecture. In a few words, such a filter consists of two parallel all pass sections, which differ in order by 1, which means that one path is of odd order while the other one is...(read more)

The Art of FPGA Design Season 2 Post 21

fpgaguru — Tue, 05 Aug 2025 02:16:34 GMT

You cannot always trust AIs I asked four major AI chat bots the same question: "What is the most efficient way to implement IIR filters? Reply in 40 words or less." Here are the responses: Perplexity AI: "Use a cascade of second-order (bi...(read more)

The Art of FPGA Design Season 2 - Post 20

fpgaguru — Thu, 31 Jul 2025 19:09:09 GMT

IIR Filters 101 I will try to keep the math side of things as light as possible but we cannot avoid it completely, so I will use the hand waving proof technique. If you have any doubts or questions about the statements made here without any proof, pl...(read more)

The Art of FPGA Design Season 2 - Post 19

fpgaguru — Sat, 26 Jul 2025 18:50:18 GMT

Why IIR Filters? Now I am going to switch gears from FIRs to their poorer and much less famous cousins, IIR filters. Recursive or Infinite Impulse Response filters tend to have a very bad reputation and are rarely used compared with Non-Recursive, Fi...(read more)

AMD Spartan UltraScale+ FPGA in action

bhfletcher — Sun, 20 Jul 2025 17:50:09 GMT

It's Alive! If you haven't had a chance to see the AMD Spartan UltraScale+ FPGA in action, here is a great opportunity. The AMD SCU35 board has the XCSU35P device on it. While not released to the public yet, we have many that are working with early a...(read more)