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RE: Lattice iCE40UP5K-EVB Evaluation Board - Part 2: Using the DSP Multiplier

shabaz — Mon, 30 Mar 2026 12:13:38 GMT

Nice work! And that looks like a great dev board for experimenting/learning.

RE: Lattice iCE40UP5K-EVB Evaluation Board - Part 2: Using the DSP Multiplier

Jan Cumps — Mon, 30 Mar 2026 11:40:24 GMT

Where do you define that it uses the DSP IP block?

note to self: It's been too long since I last used VHDL, and I'm losing the knowledge fast.

RE: Lattice iCE40UP5K-EVB Evaluation Board Outputing Audio Sine Waves Over an Optical S/PDIF Interface

kmikemoo — Sun, 22 Mar 2026 23:31:03 GMT

Very cool. Glad that you got to use your Lattice Eval Board. It's always good to finally get to those things that have been on the Project List for a while.

RE: Lattice iCE40UP5K-EVB Evaluation Board Outputing Audio Sine Waves Over an Optical S/PDIF Interface

DAB — Sat, 21 Mar 2026 20:33:59 GMT

Nice post.

RE: Fast VHDL CORDIC Sine and Cosine Component on Lattice XP2 Device Using Diamond 3.12 Part 2

scottiebabe — Wed, 18 Feb 2026 16:04:42 GMT

Very neat, I am experimenting with running an sdr on a pico and eventually will have to pick a fast atan2 approximation

RE: Fast VHDL CORDIC Sine and Cosine Component on Lattice XP2 Device Using Diamond 3.12 Part 2

DAB — Tue, 17 Feb 2026 20:32:17 GMT

Nice update.

RE: Fast VHDL CORDIC Sine and Cosine Component on Lattice XP2 Device Using Diamond 3.12 Part 2

michaelkellett — Tue, 17 Feb 2026 10:23:13 GMT

Nice to see an FPGA project at the register level in VHDL.

Good luck with the iCE40 - its a useful part - (I just did a customer design on one recently) but pretty weedy by modern FPGA standards.

On the other hand they are cheap, available in 48 pin QFN packages and use almost no power.

RE: FPGA and DSP ep. 4: Polyphase Filters

Stuart_S — Sat, 08 Nov 2025 23:51:00 GMT

There's a link to a nice VHDL resource in the tubes.

RE: Booting ZUB1CG with AES-ACC-DPEMMC-G

tjaekel — Sun, 31 Aug 2025 19:59:54 GMT

Please, have you tried in a similar way with flashing and booting PYNQ (not just a PetaLinux) from it?

It works a bit for me with PYNQ, but still not all features working in a Python script (e.g. using AXI Intc with a syncing and interrupt signal).

How to boot and run PYNQ from eMMC?

RE: The Art of FPGA Design Season 2 Post 29

DAB — Thu, 28 Aug 2025 20:40:19 GMT

Very good post on DSP implementation.

RE: The Art of FPGA Design Season 2 Post 28

flyingbean — Wed, 27 Aug 2025 17:37:39 GMT

It is enjoyable to read your blogs after a busy day.

RE: The Art of FPGA Design Season 2 Post 28

DAB — Thu, 21 Aug 2025 19:17:17 GMT

Great series, thanks.

RE: The Art of FPGA Design Season 2 Post 27

DAB — Tue, 19 Aug 2025 19:41:59 GMT

Very infomative.

RE: The Art of FPGA Design Season 2 Post 27

michaelkellett — Tue, 19 Aug 2025 08:52:42 GMT

Thanks for this series of v. interesting filter articles.

RE: The Art of FPGA Design Season 2 Post 24

DAB — Mon, 11 Aug 2025 20:15:44 GMT

Very nice post.

Takes me back to many years of DSP work.