<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>The Art of FPGA Design Season 2 - Post 3</title><link>/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-3</link><description>The basic building blocks on the FPGA implementation side The three main FPGA building blocks that are being used to implement the adders, multipliers and delays of DSP algorithms in hardware are completely different, the 6-input look up table, ...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: The Art of FPGA Design Season 2 - Post 3</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-3</link><pubDate>Tue, 01 Dec 2020 19:58:43 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:06a4b6b2-520a-47b6-aa9f-fdb82291dccb</guid><dc:creator>DAB</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Nice overview of the filter set up.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;DAB&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=10177&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>