/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-4Register pushing and the pipeline cut It should be clear by now that a direct implementation of the DSP algorithm is not good enough. Every single individual computation block, the adders and the multipliers, will require pipeline registers and ...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-4Tue, 01 Dec 2020 20:01:54 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:877dad64-d4c3-4ab8-8d6c-91bdf4a9977eDAB0<p>I am glad that you are brining up the timing issues with the pipeline.</p><p>I have seen many interesting results of DSP implementation when someone failed to properly set up the timing.</p><p>&nbsp;</p><p>DAB</p><img src="https://community.element14.com/aggbug?PostID=10215&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">