ZYNQ Stereo Camera Platform - Part2 stereolbm with Vitis Vision libraries/technologies/fpga-group/b/blog/posts/zynq-stereo-camera-platform---part2-stereolbm-with-vitis-vision-librariesThis project details how to build a stereo depth camera with AI capabilities on a ZYNQ MPSOC platform. This time we&#39;ll see how to use the Vitis Vison layer L1 libraries and PYNQ framework to implement a complete stereo depth pipeline.There a...en-USTelligent Community 12RE: ZYNQ Stereo Camera Platform - Part2 stereolbm with Vitis Vision librarieshttps://community.element14.com/technologies/fpga-group/b/blog/posts/zynq-stereo-camera-platform---part2-stereolbm-with-vitis-vision-librariesSun, 27 Oct 2024 21:47:15 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:26645591-09d7-4a38-89c5-26de32547d5cttaa0<p>Hello. Thank you for sharing your work; I&rsquo;m implementing something similar, and it has been very helpful. However, when I tried running the notebook I found in the repository you shared, I couldn&rsquo;t get past the wait() in the DMA transfer. Have you encountered the same issue?<br />Thanks.</p><img src="https://community.element14.com/aggbug?PostID=10349&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">