/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-7The Single Rate odd-symmetric FIR In the last post we have examined the even-symmetric FIR, a filter of order N=2*K. The main conclusion was that we only need K DSP48s to implement such a filter, and we came up with a basic building block that i...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-7Sun, 18 May 2025 12:00:04 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:a3f1a1e1-63f7-449e-9a29-540e928614bescotthuynh0<p>I went with the design that removes the final pre-adder, making the centre tap stage look &quot;odd&quot;. See my VHDL implementation on <a href="https://github.com/scottshuynh/art-of-fpga-season-2/tree/main/post_7_single_rate_odd_symmetric_fir" rel="noopener noreferrer nofollow" target="_blank" data-e14adj="t">Github</a>.</p><img src="https://community.element14.com/aggbug?PostID=10375&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-7Tue, 01 Dec 2020 20:10:34 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:a3f1a1e1-63f7-449e-9a29-540e928614beDAB0<p>Nice update.</p><p>&nbsp;</p><p>DAB</p><img src="https://community.element14.com/aggbug?PostID=10375&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">