/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-8The Single Rate symmetric FIR, low latency transposed architecture The question we need to answer now is this - for those applications that require very low latency FIRs is there a way to avoid the increase in latency proportional to the filter ...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-8Tue, 13 Jun 2023 08:33:06 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7527b9ac-5208-4627-bde7-c24bf3be6003Need4Speed1<p>Hi, thank you for the great sharing in this blog. A question here hopes to get some advice. For&nbsp;<span>single rate odd symmetric FIR filter where the sample rate is a sub-multiple of the FPGA clock rate. For example, a sample rate of 200kHz and the&nbsp;DSP48 slice and fabric running at 400MHz. In this case, if a low latency FIR design is required. What are the things need to consider in order to achieve low latency. Is the pipelining method and the same transposed architecture&nbsp;mentioned in this blog can be used?</span></p><img src="https://community.element14.com/aggbug?PostID=10414&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">