RE: The Art of FPGA Design Season 2 - Post 11

fpgaguru — Sun, 31 Jan 2021 16:09:32 GMT

Hi Rod,

There are three main ways you can do DSP hardware design with FPGAs.

1. Classic HDL design flow, using either Verilog (or rather SystemVerilog) or VHDL

2. With SysGen, which requires Matlab and Simulink from Mathworks

3. Using HLS, which means programming in C/C++

All three require of course Vivado if you are targetting a Xilinx FPGA but that's free if you can live with the limited number of parts supported by the free edition. Note that there are no other limitation, the free edition is a full blown one and includes SysGen and HLS.

The first option requires HDL design expertise. It is the best one if you want to maximize the performance of your design implementation. The second option is not free, but Mathworks provides a version of Matlab and Simulink for personal use for about $200. Finally, the third version, which is also free, might make sense if you have software development experience with the C/C++ languages. However, you pay a price in design size and speed and you still need to have a good understanding of hardware design principles, the idea that you take some arbitrary C code, push a button and magically get an efficient FPGA implementation is still a pipe dream.

My posts in this second season might give give you the wrong idea that you need to explicitly configure the DSP48 primitives to do DSP designs in XIlinx FPGAs, that's definitely not the case. I am going into the details of the DSP48s because the goal for this series of posts is to show how to go from a mathematical algorithm to an efficient hardware implementation, using various FIR architectures as a teaching vehicle. While understanding all these DSP48 details will do you no harm, you can still do good DSP hardware design using either one of the three flows mentioned above, without ever configuring a single DSP48 primitive. They can be inferred from behavioral HDL code or C/C++, there is a lot of free IP like FIR Compiler, FFTs and so on which you can instantiate in your HDL or in SysGen and so on.

If you tell me which one of the three design flows is the one you are most familiar with, maybe I can make further suggestions.

The main barrier into becoming an expert in this field is not the lack of tools, even if you insist on completely free. You can definitely get a board and tools for less than the price of a university course book. But this is not something that can be learned in a week or even a couple of months, it requires a lot of time and effort. Maybe not the proverbial 10,000 hours, but not a lot less than that either.

Catalin

RE: The Art of FPGA Design Season 2 - Post 11

14rhb — Tue, 26 Jan 2021 16:30:17 GMT

Hi [mention:6df0c41b821640f88ccc622506c3eacd:e9ed411860ed4f2ba0265705b8793d05]

Your latest post was very timely as I have been looking (and failing) at DSP under my roadtest USB104 A7: Artix-7 FPGA Development Board : although a complete beginner I found the topic very exciting and will be reading your series of reports closely to see what I can create. You mention in one of your posts you undertake this work yourself but have links to Xilinx and you may be best placed to help me understand a few very basic issues. As a hobbyist I'm using the free software (although I do have a Xilinx license for Vivado that came with a higher specification board).

Is the only way of credibly configuring the DSP slices to use Xilinx System Generator and Simulink ? I see some of the IP I do have available such as IIR and FIR Compiler use the DSP48 slices.

Without wanting to get you in trouble, are you aware of any open source approaches ? There seems to be several contenders for testing out the DSP algorithms such as Octave, R-Studio maybe, Scibus. I guess the missing part is creating a verilog script from those packages that makes use of the DSP slices in the 7-series FPGAs ?

As mentioned, I'm a novice here but pointers to material would be greatly appreciated to allow me to experiment with these powerful devices.

Thanks