<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>The Art of FPGA Design Season 2 - Post 14</title><link>/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-14</link><description>Polyphase Decimators The Polyphase Decimator FIR is the dual structure of the Polyphase Interpolator. The basic idea is that you can reduce the sample rate of a signal by a factor of M if you keep only one out of every M samples. This only works...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>