/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-16Multichannel and Overclocking FIRs - The Single Rate non-Symmetric Case We are looking now at the case of the single rate FIR filter where the sample rate is a sub-multiple of the FPGA clock rate. For example, let's say that the input ...en-USTelligent Community 12